Họ và tên: Lê Hồng Phú

MSSV: 41801040

Bài tập 6 - buổi học 20211030

5.1
a/

b/

entity bai1 is
port (CLK, X1, X2 : in bit;
Z1, Z2 ; out bit);
end bai1;
architecture bailam of bai1 is
 type states is {S0, S1, S2, S3};
signal state, next_state : states;
begin
process (X1, X2, state)
begin
Z1 <= ‘0’; Z2 <= ‘0’;
case state is
when S0 => if (X1 = ‘0’) then
if (X2 = ‘0’) then
next_state <= S3;
else
next_state <= S2;
end if;
else
if (X2 = ‘0’) then
Z1 <= ‘1’;
Z2 <= ‘1’;
next_state <= S1;
else
Z2 <= ‘1’;
next_state <= S0;
end if
end if;
when S1 => if (X1 = ‘0’) then
Z1 <= ‘1’;
if (X2 = ‘0’) then
next_state <= S0;
else
next_state <= S1;
end if;
else
Z1 <= ‘1’; Z2 <= ‘1’;
if (X2 = ‘0’) then
next_state <= S2;
else
next_state <= S3;
end if
end if;
when S2 => if (X1 = ‘0’) then
if (X2 = ‘0’) then
next_state <= S3;
else
Z1 <= ‘1’;
next_state <= S0;
end if;
else
next_state <= S1;
Z2 <= ‘1’
if (X2 = ‘0’) then
Z1 <= ‘1’;;
end if
end if;
when S3 => if (X1 = ‘0’) then
next_state <= S2;
else
if (X2 = ‘0’) then
Z2 <= ‘1’;
next_state <= S1;
else
Z2 <= ‘1’;
next_state <= S0;
end if
end if;
end case;
end process;
process (CLK)
begin
if (CLK = ‘1’ and CLK’event) then
state <= next_state;
end if;
 end process;
end bailam;
5.2
5.15
a/
library ieee;
use ieee.std_logic_1164.all;

entity bai3 is
port (
X1,X2,X3,CLK : in bit;
Z1,Z2,Z3 : out bit;
);
end bai3;

architecture bailam3 of bai3 is

signal state : bit_vector(1 downto 0);
signal nextstate : bit_vector(1 downto 0);
begin
process
begin
state <= "00";
nextstate <= "00";
wait;
end process;

process (state, X1, X2, X3)

begin
Z1 <= '0';
Z2 <= '0';
Z3 <= '0';
case state is
when "00" =>
if (X1 = '1') then
nextstate <= "01";
else
Z2 <= '1';
 If (X2 = '1') then
Z3 <= '1';
end if;
if (X3 = '1') then
nextstate <= "10";
else
nextstate <= "01";
end if;
end if;
when "01" =>
nextstate <= "00";
Z1 <= '1';
when "10" =>
if (X2 = '1') then
nextstate <= "10";
else
Z1 <= '1';
if (X1 = '1') then
nextstate <= "00";
else
Z3 <= '1';
nextstate <= "01";
end if;
end if;
when orthers =>
end case;
end process;

process (CLK)
begin
if(CLK'EVENT and CLK = '0') then
state <= nextstate;
end if;
end process;
end bailam3;