Automatisme de porte de garage

1- Etude du système sans sécurité :

CMD=’’00'’ Bou=’0'
LED=’’00" RAZ=’1'

A
Bou=’1' and FB=’1' Bou=’1' and FH=’1'

FH=’1' FB=’1'
CMD=’’11'’ M D CMD=’’01'’
LED=’’10" LED=’’01"

FH=’0' FB=’0'

library ieee;
use ieee.std_logic_1164.all;
entity porte is
port(CLK,RAZ,Bou,FH,FB: in std_logic;
CMD,LED: out std_logic_vector(1 downto 0));
end porte;

architecture arch of porte is

type state is (A,M,D);
signal etat : state;
begin
process(clk,RAZ)
begin
if (RAZ = '1') then
etat <= A;
elsif(clk'event and clk ='1') then
case etat is
when A => if(Bou ='1' and FH ='1') then
etat <= D;
elsif (Bou = '1' and FB = '1') then
etat <= M;
end if;
when M => if (FH ='1') then
etat <= A;
end if;
when D => if (FB = '1') then
etat <= A;
end if;
end case;
end if;

1
 end process;

process(etat)
begin
case etat is
when A => CMD <= "00";LED <= "00";
when M => CMD <= "11";LED <= "10";
when D => CMD <= "01";LED <= "01";
end case;
end process;

end arch;

2- Etude d’une sécurité simple :

CMD=’’00'’ Bou=’0'
LED=’’00" RAZ=’1'

A
Bou=’1' and FB=’1' Bou=’1' and FH=’1'

FH=’1' FB=’1'
CMD=’’11'’ M D CMD=’’01'’
LED=’’10" Bou=’1' and CMD(1)=’1' LED=’’01"
Bou=’1' and CMD(1)=’0'

FH=’0' FB=’0'
URG=’1' URG=’1'

Bou=’0'

library ieee;
use ieee.std_logic_1164.all;
entity porte is
port(CLK,RAZ,Bou,FH,FB,URG: in std_logic;
CMD,LED: out std_logic_vector(1 downto 0));
end porte;

architecture arch of porte is

type state is (A,M,D,U);
signal etat : state;
signal CMD_s, LED_s: std_logic_vector(1 downto 0);

2
begin
process(clk,RAZ)
begin
if (RAZ = '1') then
etat <= A;
elsif(clk'event and clk ='1') then
case etat is
when A => if(Bou ='1' and FH ='1') then
etat <= D;
elsif (Bou = '1' and FB = '1') then
etat <= M;
end if;
when M => if(URG='1') then
etat <= U;
elsif (FH ='1') then
etat <= A;
end if;
when D => if(URG='1') then
etat <= U;
elsif (FB = '1') then
etat <= A;
end if;
when U => if(Bou ='1' and CMD_s(1)='0') then
etat <= D;
elsif (Bou ='1' and CMD_s(1)='1') then
etat <= M;
end if;
end case;
end if;
end process;

process(etat)
begin
case etat is
when A => CMD_s <= "00";LED_s <= "00";
when M => CMD_s <= "11";LED_s <= "10";
when D => CMD_s <= "01";LED_s <= "01";
when U => CMD_s <= CMD_s; LED_s <= LED_s;
end case;
end process;
CMD <= CMD_s;
LED <= LED_s;
end arch;