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Membangun Finite State Machine (FSM) Dengan Pemodelan Behavioral Dalam VDHL
Membangun Finite State Machine (FSM) Dengan Pemodelan Behavioral Dalam VDHL
Membangun Finite State Machine (FSM) dengan pemodelan behavioral dalam VDHL.
Q1Q0=00
Cnt=1
Q1Q0=01
Cnt=1
Q1Q0=11
Cnt=0
Cnt=1
Q1Q0=10
3
Cnt=0
Mod-4 Up Counter
Cnt
D0
Q0
Q0'
7
7-seg Decoder
0 0
D1 Q1
Clk
Q1'
4
Cnt=0
Cnt=0 Cnt=1
Q1Q0=00
Cnt=1
Q1Q0=01
Cnt=1
Cnt=0
Cnt=0 Cnt=1
Q1Q0=00
Cnt=1
Q1Q0=01
Cnt=1
4-to-1 MUX
I3 I2 I1 I0 A B
3 2 1 0
I3 A B
I2
I1
I0
Selector F A B 0 0 1 1 0 1 0 1 F I0 I1 I2 I3
4-to-1 MUX
F = (not A and not B and I0) or (not A and B and I1) or (A and not B and I2) or (A and B and I3); Sel <= A & B; case Sel is when 00 => F <= I0; when 01 => F <= I1; when 10 => F <= I2; when 11 => F <= I3; end case;
I3 A B
I2
I1
I0
F Sel <= A & B; F <= I0 when Sel = 00 else I1 when Sel = 01 else I2 when Sel = 10 else I3;
8
4
Decoder 4-to-1 Mux 4 4 4 4 2-bit Counter
D3 D2D1 D0
Clock Divider
50Mhz