TON DUC THANG UNIVERSITY

FACULTY OF ELECTRICAL AND

ELECTRONICS ENGINEERING

402068
DIGITAL SYSTEM DESIGN 2
CHAPTER 6: TEST AND DESIGN TEST SYSTEM

.Thoai P. Vo, PhD

7 June 2016 402068 _ Chapter 6: Test and Design Test System 1
 CHAPER 6. HARDWARE TESTING AND
DESIGN FOR TESTABILITY

6.1. Test the combinational circuit

6.2. Test the sequential circuit
6.3. Scan testing
6.4. Boundary testing

7 June 2016 402068 _ Chapter 6: Test and Design Test System 2

 OBJECTIVES

• Understand the subject of testing hardware

• Use of scan techniques for testing and built-in

self-test

• design for testability in the design process so

that the final hardware can be tested efficiently
and economically.

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 CHAPER 6. HARDWARE TESTING AND
DESIGN FOR TESTABILITY

6.1 Testing Combinational Logic

6.2 Scan Testing
6.3 Built-In Self-Test

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 TESTING COMBINATIONAL LOGIC

Two common types of faults are short circuits and open circuits.
1. If the input to a gate is shorted to ground, the input acts as if it
is stuck at a logic 0. If the input to a gate is shorted to a positive
power supply voltage, the gate input acts as if it is stuck at a
logic 1.
2. If the input to a gate is an open circuit, the input may act as if
it is stuck at 0 or stuck at 1, depending on the type of logic being
used.

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 TESTING COMBINATIONAL LOGIC

We can test an AND gate for s-a-0 faults by applying 1’s

to all inputs

Testing AND and OR gates for Stuck-at Faults

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 TESTING COMBINATIONAL LOGIC

Testing an AND-OR circuits

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 TESTING COMBINATIONAL LOGIC

• Due to embedded state inside flip-flops, it is difficult to

employ the same methods as with combinational logic
• Alternative approach: design for test
• Scan Path technique: FF inputs pass through
multiplexer stages to allow them to be used in normal
mode as well as a special test shift register mode

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 CHAPER 6. HARDWARE TESTING AND
DESIGN FOR TESTABILITY

6.1 Testing Combinational Logic

6.2 Scan Testing
6.3 Built-In Self-Test

7 June 2016 402068 _ Chapter 6: Test and Design Test System 9

 SCAN TESTING

• Configure FFs into shift register

Combinational mode (red path)
Logic • Scan in test pattern of 0s and
1s
• Non-state inputs can also be
on the scan path (think
synchronous Mealy Machine)
• Run system for one clock cycle
in “normal” mode (black path)
—next state captured in scan
path
• Return to shift register mode
and shift out the captured state
and outputs

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 SCAN TESTING

Scan Path example

• w,y1,y2 test vector 001
w Y1
• Scan 01 into y1, y2 FFs
Y2

z Scan-out

y1 0
D Q
1

Q
y2
D Q 0
1

Q
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 SCAN TESTING

Scan Path example

• w,y1,y2 test vector 001
w Y1
Scan 01 into y1, y2 FFs
Y2

z Scan-out

y1 0
D Q 0
1

Q
y2
D Q 0
0 1

Q
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 SCAN TESTING

Scan Path example

• w,y1,y2 test vector 001
w Y1
Scan 01 into y1, y2 FFs
Y2

z Scan-out

y1 0
D Q 0
0 1

Q
y2
D Q 0
1 1

Q
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Scan-in G/S
 SCAN TESTING

Scan Path example

• w,y1,y2 test vector 001
w0 Y1
Scan 01 into y1, y2 FFs
Normal w=0 Y2

z Scan-out

y1 0
D Q 0
0 1

Q
y2
D Q 0
1 1

Q
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Scan-in G/S
 SCAN TESTING

Scan Path example

0
w,y1,y2 test vector 001
w0 Y1
Scan 01 into y1, y2 FFs
0
Normal w=0 Y2
Output z=0, Y1=0, Y2=0

0 Scan-out
z

y1 0
D Q
0 1

Q
y2
D Q 0
1 1

Q
7 June 2016 402068 _ Chapter 6: Test and Design Test System 15

Scan-in G/S
 CHAPER 6. HARDWARE TESTING AND
DESIGN FOR TESTABILITY

6.1 Testing Combinational Logic

6.2 Scan Testing
6.3 Built-In Self-Test

7 June 2016 402068 _ Chapter 6: Test and Design Test System 16

 BUILT-IN SELF-TEST
x0 P0
. .
Test . Circuit . Test
Vector . Under . Response
xn-1 Pm-1
Generator Test Compressor
Signature

Test Vector Generator

Pseudorandom tests with a feedback shift register
Seed generates a sequence of test patterns
Outputs combined using the same technique
Generates a unique signature that can be checked to
determine if the circuit is correct

7 June 2016 402068 _ Chapter 6: Test and Design Test System 17

 BUILT-IN SELF-TEST

Linear Feedback Shift Register

D Q D Q D Q D Q

Q Q Q Q

Random Test Pattern

P D Q D Q D Q D Q

Input from Q Q Q Q
circuit under test

Signature
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 BUILT-IN SELF-TEST
Linear Feedback Shift Register
f
D Q D Q D Q D Q

Q Q Q Q

Initial Configuration x3 x1
x2 x0

x3 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1
x2 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0 0 …
x1 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0 0
x0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 1 0
f 1 1 1 0 1 0 1 1 0 0 1 0 0 0 1 1 …

• Starting with the pattern 1000, generates 15 different

patterns in sequence and then repeats
• Pattern 0000 is a no-no
7 June 2016 402068 _ Chapter 6: Test and Design Test System 19
 SUMMARY AND ASSIGNMENT
• In this chapter, we have introduced:
The subject of testing hardware
The use of scan techniques for testing and built-in
self-test
testability in the design process so that the final
hardware can be tested efficiently and economically

• Assignments: 10-1 to 10-5 pages 501-502 [1].

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