FPGA Based System Design

ENGR. RASHID FARID CHISHTI

LECTURER,DEE, FET, IIUI
CHISHTI@IIU.EDU.PK

WEEK 2

MEMORY AND PROGRAMMABLE LOGIC

www.iiu.edu.pk 2/10/21
 Memory and Programmable Logic Devices
2

Random Access Memory (RAM)

Simple Programmable Logic Devices (SPLDs)
 Programmable Read Only Memory (PROM)
 Programmable Array Logic (PAL)
 Programmable Array Logic (PAL) (One Time Programmable)
 Generic Array Logic (GAL) (Reprogrammable)
 Programmable Logic Array (PLA)

www.iiu.edu.pk 2/10/21
 Random Access Memory (RAM)
3

www.iiu.edu.pk 2/10/21
 4

Select R/W ’ Input Q Output Operation

0 0 0 Q(t) 0 No Operation Select R/W’ Operation
0 0 1 Q(t) 0 No Operation
0 1 0 Q(t) 0 No Operation 0 X No
Operation
0 1 1 Q(t) 0 No Operation
1 0 0 0 0 Write 0 1 0 Memory
Write
1
1
0
1
1
0
1
Q(t)
0
Q(t)
Write 1
Read Data
1 1 Memory
Read
1 1 1 Q(t) Q(t) Read Data
www.iiu.edu.pk 2/10/21
 2-to-4 Decoder
5

En w1 w0 y0 y1 y2 y3 w 1 w0

1 0 0 1 0 0 0
1 0 1 0 1 0 0
1 1 0 0 0 1 0
1 1 1 0 0 0 1
y0
0 x x 0 0 0 0
(a) Truth table
y1

y2
w0 y0
w1 y1 y3
y2
En y3

En
(b) Graphic symbol
(c) Logic circuit

www.iiu.edu.pk 2/10/21
 6

www.iiu.edu.pk 2/10/21
 Bus Size in RAM
7

Question: How many address lines, input-output data lines are needed in each
case of RAM size
(a) 8K×16 (b) 2G×8 (c) 16M×32 (d) 256K×64

RAM Size: (a) 214 Bytes (b) 231 Bytes (c) 226 Bytes (d) 221 Bytes

www.iiu.edu.pk 2/10/21
 Basic Types of RAM
8
Static RAM (SRAM) Dynamic RAM (DRAM)
Stores data in latches Stores data in capacitors
No refreshing Needs refreshing
More power Reduced power
consumption consumption
Less storage capacity Large storage capacity
Used in Microprocessor Used in PC memory on
cache memory Mother Board
volatile volatile

www.iiu.edu.pk 2/10/21
 Simple Programmable Logic Devices (SPLDs)
9

www.iiu.edu.pk 2/10/21
 Simple Programmable Logic Devices (SPLDs)
10

PROM (Programmable Read Only Memory)

PROM has fixed AND array constructed as decoder and a
programmable OR array.
The programmable OR gates implement the Boolean
functions in sum of min terms form.
Initially PROM contains all the fuses intact, giving all 1’s.
Fuses are blown by application of high voltage pulse.
A blown fuse defines a binary 0 state and an intact fuse
gives a binary 1 state.

www.iiu.edu.pk 2/10/21
 (SPLDs) - PROM
B A
11

Blow the Fuse

for logic 0
A'B'

A B'

A'B

A B
×

Keep the Fuse

for logic 1 A3 A2 A1 A0

www.iiu.edu.pk 2/10/21
 Logic Implementation in PROM
12

Question: Implements the following in PROM

A3 = A'B', A2 = A'B' + AB, A1 = (AB)', A0 = A+B
Answer: Convert all equations into sum of minterms
A3 = A'B'
A2 = A'B'+ AB
A1 = (AB)' = A'+B' = A'(B+B')+B'(A+A')
= A'B+ A'B'+ AB'+ A'B'
= A'B + AB' + A'B'
A0 = A+B = A(B+B')+B(A+A')= AB+AB'+AB+A'B
= AB + AB' + A'B
www.iiu.edu.pk 2/10/21
 Logic Implementation in PROM
B A
13

A'B'
× × ×
A B'
× ×
A'B
× ×
A B
× ×

A3 A2 A1 A0

www.iiu.edu.pk 2/10/21
 Types of ROMs
14

1. Mask-programmable ROM
 Data is permanently stored (include or omit the switching elements)
 Economically feasible for a large quantity
2. PROM - Programmable ROM
 For logic 0 blow the fuse at high voltage
3. EPROM – Erasable PROM
 PROM programmer is used to provide appropriate voltage
 Data is permanent until erased using an ultraviolet light
4. EEPROM – Electrically EPROM
 Erased using electric signals
 FLASH Memory is similar to EEPROM, can do in-circuit programming
 No need for separate programmer.
www.iiu.edu.pk 2/10/21
 Programmable Logic Devices (PLDs)
15

PALs (Programmable Array Logics)

The AND array is programmable; the OR array is fixed
AND array – realizes product terms of the input variables
OR array – ORs together the product terms
Simpler to manufacture, less expensive, better
performance than PLAs

www.iiu.edu.pk 2/10/21
Generic PAL Structure
16

www.iiu.edu.pk 2/10/21
 Typical PALs
17
 Typical PALs have
 from 10 to 20 inputs
 from 2 to 10 outputs
 from 2 to 8 AND gates driving each OR gate
 often include D flip-flops
Select Enable
f1
Flip-flop
D Q
Clock

To AND plane
MUX output is “fed back” to the AND plane.
www.iiu.edu.pk 2/10/21
 Logic Diagram for 16R4 PAL
18

www.iiu.edu.pk 2/10/21
 Logic Diagram for 16R4 PAL
19

www.iiu.edu.pk 2/10/21
 Programmable Logic Devices (PLDs)
20

PLAs (Programmable Logic Arrays)

Logic functions in Sum Of Product (SOP) form
Both AND and OR planes are programmable
 AND array – realizes product terms of the input
variables
 OR array – ORs together the product terms

www.iiu.edu.pk 2/10/21
 Generic PLA Structure
21

www.iiu.edu.pk 2/10/21
Logic Implementation in PLA
22

www.iiu.edu.pk 2/10/21
 Binary to Gray Code Conversion

www.iiu.edu.pk 2/10/21
A B C D W X Y Z
BCD-to-Gray-Code Converter
0 0 0 0 0 0 0 0
0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 1
24
0 0 1 1 0 0 1 0
0 1 0 0 0 1 1 0
0 1 0 1 1 1 1 0
0 1 1 0 1 0 1 0
0 1 1 1 1 0 1 1
0 0 0 0 1 0 0 1
1 0 0 1 1 0 0 0
1 0 1 0 X X X X
1 0 1 1 X X X X
1 1 0 0 X X X X
1 1 0 1 X X X X
1 1 1 0 X X X X
1 1 1 1 X X X X

www.iiu.edu.pk 2/10/21
 BCD-to-Gray-Code Converter in PLA
25

The GAL, although similar to

the PAL architecture, uses
EEPROM and can be
reconfigured.
www.iiu.edu.pk 2/10/21
 PLA v.s. PAL
26

 PLAs are more flexible than PALs since both AND & OR planes are
programmable in PLAs.
 Because both AND & OR planes are programmable, PLAs are
expensive to fabricate and have large propagation delay.
 By using fix OR gates, PALs are cheaper and faster than PLAs.
 Logic expanders increase the flexibilities of PALs, but result in
significant propagation delay.
 PALs usually contain D flip-flops connected to the outputs of OR gates
to implement sequential circuits.
 PLAs and PALs are usually referred to as SPLD.

www.iiu.edu.pk 2/10/21