2/17/2011

EE 811
Advanced Digital System Design

Dr. Arshad Aziz

Fundamental of Logic
Design

Learning Objectives
• Review the basic concepts of logic circuits
• Variables and functions
• Boolean algebra
• Minterms and maxterms
• Logic gates
• Synthesis
• Create CMOS logic gates

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x = 0 x = 1

(a) Two states of a switch

(b) Symbol for a switch

Figure 2.1. A binary switch.

S
Battery x L Light

(a) Simple connection to a battery

S
Power
supply x L

(b) Using a ground connection as the return path

Figure 2.2. A light controlled by a switch.

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S S
Power
supply x1 x2 L Light

(a) The logical AND function (series connection)

x1

Power Light
g
supply
l S L

x2

(b) The logical OR function (parallel connection)

Figure 2.3. Two basic functions.

x1 S
Power
supply S x3 L Light

x2

Figure 2.4. A series-parallel connection.

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Power
supply x S L

Figure 2.5. An inverting circuit.

Figure 2.6. A truth table for AND and OR.

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Figure 2.7. Three-input AND and OR.

Basic Gates – AND, OR, NOT

x1
x2
x1
x1  x2 x1  x2   xn
x2
xn

(a) AND gates

x1
x2
x1
x1 + x2 x1 + x2 + + xn
x2

xn

(b) OR gates

x x

(c) NOT gate

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Basic Gates – NAND, NOR

x1
x2
x1
x 1  x 2 x 1  x 2    x n
x2

xn

(a) NAND gates

x1
x2
x1
x1 + x2 x 1 + x 2 +  + x n
x2

xn

(b) NOR gates

Basic Logic Gates

Buffer AND OR EX-OR

Logic
i
A A A Function
A X X X X
B B B
Gate
X=A X = AB X=A+B X=A+B Symbol

A X A B X A B X A B X Logic
0 0 0 0 0 0 0 0 0 0 0 Expression
1 1 0 1 0 0 1 1 0 1 1
1 0 0 1 0 1 1 0 1
1 1 1 1 1 1 1 1 0
Truth
Table

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x
1
x
2 f = x + x   x
x 1 2 3
3

Figure 2.9. An OR-AND function.

1
x
1 0

x 1
2 0

1
A
0
1
B
0
1
f
0 Time
(c) Timing diagram

0 01 1 11 00

x
1
11 0 1
0 10 1 g
x
2

(d) Network that implements g = x + x

1 2

Figure 2.10b. Logic network.

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DeMorgan’s Theorem and other symbols

for NAND, NOR

x1
x1 x1
x2 x2
x2

(a) x1 x2 = x1 + x2

x1
x1 x1
x2 x2
x2

(b) x1 + x2 = x1 x2

Figure 2.11. Proof of DeMorgan’s theorem.

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Basic Gates – XOR

x1 x2 f = x1 x2

0 0 0
0 1 1
x1
1 0 1
x2 f = x1 x2
1 1 0

(a) Truth table (b) Graphical symbol

x1
x2

f = x1 x2

(c) Sum-of-products implementation

Basic Gates – XNOR

x1 x2 f = x1 x2

0 0 1
0 1 0
x1
1 0 0
x2 f = x1 x2 = x1 . x2
1 1 1

(a) Truth table (b) Graphical symbol

x1
x2

f = x1 x2

(c) Sum-of-products implementation

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Variables and Functions

x1
x2 y
Function
y=f(x1,x2...xn)
xn

• A function is defined as the dependency of output y on

the n inputs (x1, x2, …xn)
• The n inputs (x1, x2, …xn) are variables
• The function of a combinational logic circuit can be expressed by
g function
a Boolean logic
• For a Boolean logic function, output and inputs are binary,
and the basic operators include AND, OR, NOT.

Example
f ( x1 , x 2 , x3 )  x1  x 2  x3

Basic functions
• Summary of basic logic functions
• Inversion, AND, OR
• Can be used to implement logic function of any
complexity

x x

0 1

1 0

NOT

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Logic gates
• The basic logic function (operation) can be
iimplemented
l t d electronically
l t i ll with ith
transistors, which is called a logic gate
• A logic gate has one or more inputs and
one output
• schematics
x1 x1
x x x1  x2 x1 + x2
x2 x2

Truth Table
f ( x1 , x 2 , x3 )  x1  x 2  x3
Representations of a logic function:
-- mathematic Algebra expression
x1 x2 x3 y -- Truth Table
0 0 0 1 -- Karnaugh map (next page)
0 0 1 0
0 1 0 1
0 1 1 0
1 0 0 1 Observations for an n-variable function:
n
1 0 1 0 1) 2 rows in truth table
1 1 0 1 (2n)
1 1 1 2) 2 different n-variable functions totally
1

4 different 1-variable functions: f(x)=0, f(x)=1, f(x)=x, f(x)=x

16 different 2-variable functions
256 different 3-variable functions

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Karnaugh Map
x1 x2 x3
x1 x2
0 0 0 m0 x3
00 01 11 10
0 0 1 m1
0 m0 m2 m6 m4
0 1 0 m2
0 1 1 m3 1 m1 m3 m7 m5
1 0 0 m4
1 0 1 m5 (b) Karnaugh map
1 1 0 m6
1 1 1 m7

(a) Truth table

x1x2
x3
00 01 11 10
0 0 0 1 1
f = x1x3 + x2x3
1 1 0 0 1

x1 x2 x1 x2
x3 x4 x3 x4
00 01 11 10 00 01 11 10

00 00 1

01 1 1 01 1 1

11 1 1 11 1 1

10 1 1 10 1 1

x5 = 0 x5 = 1

f 1 = x1 x3 + x1 x3 x4 + x1 x2 x3 x5

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Boolean Algebra
• Axioms of Boolean Algebra
• 0•0=0,
00 0 0 0•1=0,
1 0 11•0=0,
0 0 1 1•1=1
1 1
• 0+0=0, 0+1=1, 1+0=1, 1+1=1
• If x=0, then x=1; if x=1, then x=0
• Single-Variable theorems
• X•0=0, x•1=x, x+0=x, x+1=1, x+x=1, x•x=0
• Multiple-Variable Properties
• Commutative, associative, distributive,
absorption, combining, DeMorgan’s theorem

Properties
• Commutative x y  yx

• Associative x  ( y  z)  ( x  y)  z

• Distributive x   y  z   x  y  x  z
• Absorption x  x y  x

• Combining x y  x y  x

• DeMorgan’s theorem x  y  x  y

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Synthesis using basic logic gates

• Synthesis: begin with a description of the
desired behavior
behavior, and then generate a circuit
that realizes this behavior.
• Example of synthesis

f ( x1 , x2 )  x1 x2  x1 x2  x1 x2 f ( x1 , x2 )  x2  x1

Sum-of-Products
• Minterm: any function can be expressed as the sum of
some minterms.
• For a function of n variables, a product term in which each of the n
variables appears once
• Variables either in uncomplemented or complemented form
• For a given row of a truth table, xi of xi =1, xi if xi =0
• Maxterm: any function can be expressed as the product of
some maxterms.
• For a function of n variables, a sum term in which each of the n
variables appears once
• Variables either in uncomplemented or complemented form
• For a given row of a truth table, xi of xi =0, xi if xi =1

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Three-variable minterms and

maxterms

Sum-of-Products, Product-of-sums

SOP POS

f ( x1 , x2 , x3 )   m(1,4,5,6) f ( x1 , x2 , x3 )   M (0,2,3,7)

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Transistor as a switch
• Concept of switch
• Signals are assumed to have only 2 possible
values(0,
l (0 andd 1)
• The basic element is a switch which has two states
• The switch state is controlled by an input variable x
• Switch is open if x=0; closed if x=1

Implementation of Logic gates (1)

• Transistor switches

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Implementation of Logic gates (2)

• CMOS logic gates (as networks of transistors)
V DD
VDD PUN

T1 T2
T1
Vf

Vx Vf Vx T3 x1 x2 T1 T2 T3 T4 f
1

0 0 on on off off 1
T2 0 1 on off off on 1
Vx T4 off on on off
2 1 0 1
1 1 off off on on 0
PDN
(a) Circuit (b) Truth table and transistor states

Implementation of Logic gates (3)

VDD=5V

• PUN: PMOS x1
y

• PDN:
PDN NMOS x2
Switch network

• Output Vf is GND
V DD

selectively connected
either to Vdd through
PUN or to Gnd Pull-up network
(PUN)

through PDN
PDN,
Vf
depending on inputs Vx
1
Pull-down network
(PDN)
Vx
n

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Complex CMOS logic gate

• Example 3.1 VDD

F f=1
For f 1
f  x1  x2 x3

f  x1 ( x2  x3 ) For f=0
Vf

Vx
1

Vx
2

Vx
3

Procedures for complex logic gates

• Express a function so that all variables appear in their
complemented
p form
• e.g. f ( x1 , x2 , x3 )
• Derive the PUN based on f ( x1 , x2 , x3 )
• Products  transistors (or branches) in series
• Sums  transistors (or branches) in parallel
• Derive a complemented function so that all variables
appear in their uncomplemented form
• e. g. f ( x1 , x2 , x3 )
• Derive the PDN based on f ( x1 , x2 , x3 )
• Products  transistors (or branches) in series
• Sums  transistors (or branches) in parallel

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Exercise ?
• Create CMOS gate for function
f  x1 ( x2 x3  x4 )

Analysis of complex CMOS gate

• Derive expression from circuit based on PUN
• Branches in parallel  sums
• Branches in series  products
• All variables in complemented form
• Derive PDN from PUN, or derive PUN from PDN
• For branches in parallel in PDN, there are branches in
series in PUN; vice versa.
versa
• For branches in series in PDN, there are branches in
parallel in PUN; vice versa.

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MSI Devices
• Medium Scale Integration (MSI) devices are digital devices that are build
using a few tens to hundreds of logic gates
gates.

• MSI devices are used as discrete devices packed in a single Integrated

Circuit (IC), or as building blocks for other, more complex devices such as
memory devices or microprocessors.

• Some typical MSI devices are the following:

• Encoders and Decoders

• Multiplexers and Demultiplexers

• Full Adders

• Latches and flip flops

• Registers and Counters

Examples of MSI Devices

Decimal to BCD Encoder
4-to-1 Multiplexer
DEC/BCD
I3 1 2
D0 1 0 3
1 2 3 D1
I2
D2 1
D3 Y3
4 5 6 Y2 1
D4 I1
Y1 0
D5
Y0
7 8 9 D6
1
I0
4/1 Mux
D7
D8
0 D9

BCD to Decimal Decoder

1 1 1 1 0 1 2 3 4 5 6 7 8 9

0 0 0 0

0 1 0 1 0 1 0 1
BCD/DEC
Y0
Y1
A0 Y2
Y3
A1 Y4
A2 Y5
A3 Y6
Y7
Y8
Y9

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Decoders
• A decoder is a combinational digital circuit with a number of inputs ‘n’ and a
number of outputs ‘m’, where m= 2n
• Only one of the outputs is enabled at a time. The output enabled is the one
specified by the binary number formed at the inputs of the decoder.
• On the circuit below,
below the inputs of the decoder are connected on three
switches, forming the number 5 [(101)2], thus only the lamp #5 will be ON

1 1 1 0 1 2 3 4 5 6 7

0 0 0

0 1 0 1 0 1

3/8 DEC.
Y0
Y1
A0
Y2
A1 Y3
Y4
A2
Y5
Y6
Y7

2 to 4 Line Decoder:
2-to-4 Line Decoder
2/4 DEC A1 A0 Y0 Y1 Y2 Y3 Y0 = A1 A0 Y0
Y0 0 0 1 0 0 0 Y1 = A1 A0 A1
A1 Y1
Y1 0 1 0 1 0 0 Y2 = A1 A0
A0 Y2 Y2
1 0 0 0 1 0 Y3 = A1 A0
A0
Y3 1 1 0 0 0 1 Logic Y3
Expressions
Logic Symbol Truth Table Logic Circuit

2-to-4 Line Decoder with Enable Input

2/4 DEC E A1 A0 Y0 Y1 Y2 Y3 Y0 = E A1 A0
A1 Y0
A1 Y0 0 X X 0 0 0 0
Y1 = E A1 A0
Y1
A0 Y1 1 0 0 1 0 0 0
E
Y2 = E A1 A0
Y2 1 0 1 0 1 0 0 Y2
E Y3 1 1 0 0 0 1 0 Y3 = E A1 A0 A0
Y3
1 1 1 0 0 0 1 Logic
Logic Symbol Truth Table Expressions Logic Circuit

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3 to 8 Line Decoder:
3-to-8 Line Decoder with Enable Input
3/8 DEC E A1 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y0
Y0 0 X X X 0 0 0 0 0 0 0 0
A2 Y1
Y1 1 0 0 0 1 0 0 0 0 0 0 0
A2 Y2 Y2
1 0 0 1 0 1 0 0 0 0 0 0
A1 Y3 1 0 1 0 0 0 1 0 0 0 0 0 Y3
A1
A0 Y4 1 0 1 1 0 0 0 1 0 0 0 0
Y4
Y5 1 1 0 0 0 0 0 0 1 0 0 0
Y5
Y6 1 1 0 1 0 0 0 0 0 1 0 0 A0
E Y7 1 1 1 0 0 0 0 0 0 0 1 0 Y6
1 1 1 1 0 0 0 0 0 0 0 1
Y7
E
Logic Symbol Truth Table Logic Circuit

Multiplexers
• A multiplexer is a device that has a number of data inputs “m”, and number
of control inputs “n” and one output, such that m=2n. The output has always
the same value as the data input specified by the binary number at the
control inputs.
• The rotary switch (selector) shown in figure (a) below
below, is equivalent to a 4-
4
to-1 multiplexer.
• The sliding switch shown in figure (b) below, is equivalent to an 8-to-1
multiplexer.

(a) 4-to-1 Multiplexer (b) 8-to-1 Multiplexer

1 1 0 1 0 0 1 1
I3 1 2
1 0 3

I2 I0 I1 I2 I3 I4 I5 I6 I7
1
1
I1
0
Y 8/1 Mux
I0
1 4/1 Mux
0

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Internal structure of a 2-to-1

multiplexer.
• The design of a 2-to-1 multiplexer is shown below.
• If S=0 then the output “Y” has the same value as the input “I0”
• If S=1 then the output “Y” has the same value as the input “I1”

2-to-1 Multiplexer
2/1 MUX S I1 I0 Y
I0
I0 0 0 0 0
Y I1I0
I1 0 0 1 1 S 00 01 11 10 1/2 Dec.

S 0 1 0 0 0 0 1 1 0 S Y
Logic Symbol 0 1 1 1 1 0 0 1 1
1 0 0 0
S Y 1 0 1 0 I1
Y= S I0 + S I1
0 I0 1 1 0 1
1 I1 1 1 1 1
Logic Expression Logic Circuit
Logic Function Truth Table

1-bit Full Adder

8/1 Mux
A B Cin Cout Sum A 0 I0
Sum 0 I1
0 0 0 0 0
0 0 1 0 1 B 0 I2
0 1 0 0 1 1 I3
Cin Y Cout
0 1 1 1 0 0 I4 4/1 Mux
Cout
1 0 0 0 1 1 I5 0 I0
1 0 1 1 0 1 I6 A I1
1-Bit Full Adder using gates Y Cout
1 1 0 1 0 1 I7 A I2
S2 S1 S0 1 I3
1 1 1 1 1
3/8 Dec. A S1 S0
A
Truth Table A Y0 B B
B B Y1 Cin
Cin
C Y2 S2 S1 S0
Cin
Y3 0 I0
S1 S0
A B Cin Y4 1 I1 A I0
Y5 1 I2 A' I1
1-Bit F.A. En Y Sum
Y6 0 I3 A' I2
Y Sum
Y7 1 I4 A I3
Cout Sum
0 I5 4/1 Mux
0 I6 1-Bit Full Adder using 4/1 multiplexers
Logic Symbol Cout Sum 1 I7
8/1 Mux
1-Bit Full Adder using a decoder 1-Bit Full Adder using 8/1 multiplexers

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4-bit Full Adder (Ripple-Carry Adder)

• To obtain a 4-bit full adder we cascade four 1-bit full adders, by connecting
the Carry Out bit of bit column M to the Carry In of the bit column M+1, as
shown below. The Carry In of the Least Significant column is set to zero.

A3 B3 A2 B2 A1 B1 A0 B0

A B Cin A B Cin A B Cin A B Cin

1-Bit F.A. 1-Bit F.A. 1-Bit F.A. 1-Bit F.A.
Cout Sum Cout Sum Cout Sum Cout Sum

Cout
S3 S2 S1 S0

• Example: Find the bit values of the outputs {Cout,S3..S0} of the full adder
shown below, if {A3..A0 = 1011} and {B3..B0 = 0111}.

Magnitude Comparator

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The D Edge Triggered Flip Flop

The D edge triggered flip flop can be obtained by connecting the J with
the K inputs of a JK flip through an inverter as shown below. The D
edge trigger can also be obtained by connecting the S with the R inputs
of a SR edge triggered flip flop through an inverter.

Positive Edge D Flip Flop Negative Edge D Flip Flop

D J Q Q D J Q Q

CLK CLK

K Q Q K Q Q

Logic Symbol CLK D QN+1 Function Logic Symbol CLK D QN+1 Function
D Q X Q D Q X Q
CLK 0 CLK 0
0 0
Q Q 1
1 1 1

The Toggle (T) Edge Triggered Flip Flop

The T edge triggered flip flop can be obtained by connecting the J with
the K inputs of a JK flip directly. When T is zero then both J and K are
zero and the Q output does not change. When T is one then both J and
K are one and the Q output will change to the opposite state, or toggle.

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Flip Flops with asynchronous inputs (Preset and Clear)

Two extra inputs are often found on flip flops, that either clear or preset
the output. These inputs are effective at any time, thus are called
asynchronous. If the Clear is at logic 0 then the output is forced to 0,
irrespective of the other normal inputs. If the Preset is at logic 0 then
the output is forced to 1, irrespective of the other normal inputs. The
preset and the clear inputs can not be 0 simultaneously. In the Preset
and Clear are both 1 then the flip flop behaves according to its normal
truth table. Positive Edge JK Flip Flop with Preset and Clear

CLK PR CLR J K QN+1 Function

PRESET
PR
0 0 X X
J Q
0 1 X X 1
1 0 X X 0
K Q 1 1 0 0 Q
CLR
1 1 0 1 0
CLEAR
1 1 1 0 1
1 1 1 1 Q’

JK Flip Flop With Preset and Clear:- Example

Complete the timing diagrams for :
(a) Positive Edge Triggered JK Flip Flop
(b) Negative Edge Triggered JK Flip Flop.
Assume that for both cases the Q output
p is initially
y at logic
g zero.
(a) (b)

CLK CLK

J J

K K

CLR CLR

PR PR

Q Q

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Sequential circuit example 1

A0

2-to-1 SET
MUX
D Q

A1

CLR Q

Clock

1 2 3 4 5 6 7 8 9 10
Clock

A0

A1

D
Q

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Homework
• Problem 2.6 to 2.10
• Problem 2.7 to 2.11

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