Finite State Machine

Example: Sequence Detector

 Example
The system detects sequence of ‘0110’ on a
single input ‘b’ to the system, and asserts ‘1’ on
output ‘x’ for one cycle. Otherwise, output ‘x’
remains ‘0’.

B 0 0 1 0 1 1 0 0 1 0 0 1 0 1 1 0 0 1 1 0 0

x 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 1 0 0 0 1
 State Diagram
B=1

S0
X=0
B=1 B=0 B=0

B=1 B=0 S1
S4
X=0
X=1
B=0

B=1

B=0
S2
S3 X=0
X=0 B=1
 State Diagram
B=1

S0
X=0
B=0 B=0
B=1

B=0 S1
B=1 S4
X=0
X=1
B=0

B=1

B=0
S2
S3 X=0
X=0 B=1
Green Shows Successful Detection Path
Red Show Unsuccessful Detection Path
Blue First Successful Detection of Next Sequence
Orange First Unsuccessful detection of Next Sequence
 Circuit Diagram

X
B

NextState
State
 Verilog Code
module SeqDetect( input b, input clk, input reset, output reg x );
parameter S0=0, S1=1, S2=2, S3=3, S4=4;
reg [2:0] State, StateNext;
Inputs in the sensitivity list
//Comb Block B
always @(State, b) begin X
case(State) State
S0: begin
x<=0;
if(b==0) NextState
StateNext <= S1;
else
StateNext <=S0; Outputs are being assigned
end
S1: begin
x<=0;
if(b==0)
StateNext <= S1;
else
StateNext <= S2;
end
 S2: begin
x<=0;
if(b==0)
StateNext <= S1;
else
StateNext <= S3;
end
S3: begin
x<=0;
if(b==0)
StateNext <= S4;
else
StateNext <= S0;
end
S4: begin
x<=1;
if(b==0)
StateNext <= S1;
else
StateNext <= S0;
end
endcase
end
always @(posedge clk)begin
if(reset ==1)
State <= S0; State
else
State <= StateNext; NextState
end
endmodule