EX NO: SEQUENCE GENERATOR/DETECTOR

DATE:

AIM:

To design a sequence generator and detector for a given sequence using Verilog HDL in
cadence.

SOFTWARE USED:

Cadence

SOURCE CODE: MEALY NON OVERLAPPING:

module mealeynon(x,j,k,clk,rst,q,qb,y);
input x,clk,rst;
input [1:0]j,k;
output [1:0]q,qb;
output y;
wire w1,w2,w3;
jkff g1(j[0],k[0],clk,rst,q[0],qb[0]);
jkff g2(j[1],k[1],clk,rst,q[1],qb[1]);
and g3(j[0],x,q[1]);
or g4(k[0],q[1],0);
and g5(w1,x,qb[0]);
not g6(w2,x);
and g7(w3,w2,q[0]);
or g8(j[1],w1,w3);
or g9(k[1],q[1],0);
and g10(y,x,q[0],q[1]);
endmodule
module jkff(j,k,clk,rst,q,qb);
input j,k,clk,rst;
output reg [3:0]q,qb;
wire j,k,clk,rst;
always@(posedgeclk)
begin
if(rst)
begin
q<=0;
STATE DIAGRAM:

STATE TABLE:

PRESENT NEXT STATE OUTPUT

STATE X=0 X=1 X=0 X=1

S0 S0 S1 0 0

S1 S0 S2 0 0

S2 S3 S2 0 0

S3 S0 S0 0 1

TRANSITION TABLE:

PRESENT NEXT STATE OUTPUT

TABLE X=0 X=1 X=0 X=1

00 00 01 0 0

01 00 10 0 0

10 11 10 0 0

11 00 00 0 1
qb<=1;

end
else begin

if(j!=k)
q<=j;
qb<=k;
end
else if(j==1&&k==1)
begin
q<=~q;
qb<=~qb;
end
end
end
endmodule

MEALY OVERLAPPING:

module mealeyover(x,j,k,clk,rst,q,qb,y);
input x,clk,rst;
input [1:0]j,k;
inout [1:0]q,qb;
output y;
wire w1,w2,w3,w4;
jkff g1(j[0],k[0],clk,rst,q[0],qb[0]);
jkff g2(j[1],k[1],clk,rst,q[1],qb[1]);
and g3(j[0],x,q[1]);
or g4(k[0],q[1],0);
and g5(w1,x,qb[0]);
not g6(w2,x);
and g7(w3,w2,q[0]);
or g8(j[1],w1,w3);
and g9(w4,w2,q[0]);
or g10(k[1],w4,qb[0]);
and g11(y,x,q[0],q[1]);
endmodule
module jkff(j,k,clk,rst,q,qb);
input j,k,clk,rst;
output reg [3:0]q,qb;
wire j,k,clk,rst;
EXCITATION TABLE:

PRESENT STATE NEXT STATE OUTPUT

X=0 X=1 X=0 X=1
Q0Q1 J0K0 J1K1 J0K0 J1K1

00 0X 0X 0X 1X 0 0

01 0X X1 1X X1 0 0

10 X0 1X 0X 0X 0 0

11 X1 X1 X1X1 0 1

K-MAP:
X/Q1Q2

0 0 X X

0 1 X 0
J1=XQ2
x/Q1Q2
X X 1 0

X X 1 0
K1=Q2
x/Q1Q2

0 X X 1

1 X X 0
J2=XQ1b+XbQ1
always@(posedgeclk)

begin
if(rst)

begin
q<=0;

qb<=1;

end

else begin

begin
q<=j;
qb<=k;
end
else if(j==1&&k==1)
begin
q<=~q;
qb<=~qb;
end
end
end
endmodule

MOORE NONOVERLAPPING:
module moorenon(x,j,k,clk,rst,q,qb,y);
input x,clk,rst;
input [2:0]j,k;
inout [2:0]q,qb;
output y;
wire w1,w2,w3,w4,w5;
jkff g1(j[0],k[0],clk,rst,q[0],qb[0]);
jkff g2(j[1],k[1],clk,rst,q[1],qb[1]);
jkff g3(j[2],k[2],clk,rst,q[2],qb[2]);
and g4(j[0],q[0],qb[1],qb[2]);
and g5(w1,q[0],qb[1],qb[2]);
or g6(k[0],qb[0],w1);
and g7(j[1],qb[0],q[2]);
and g8(w2,qb[0],qb[1],x);
or g9(k[1],w2,w1);
and g10(w3,qb[0],qb[2],x);
not g11(w4,x);
 X/Q1Q2
X Q1Q2
x 1 1 0 0 0 0 0

x 1 1 0 0 0 1 0
K2=Q2
Y=XQ1Q2

LOGIC DIAGRAM:
 and g12(w5,qb[0],q[2],w4);
or g13(j[2],w1,w3,w5);
or g14(k[2],w1,qb[0]);
or g15(y,qb[2],0);
endmodule
module jkff(j,k,clk,rst,q,qb);
input j,k,clk,rst;
output reg [3:0]q,qb;
always@(posedgeclk)
begin
if(rst)
begin
q<=0;
qb<=1;
end
else begin
if(j!=k)
begin
q<=j;
qb<=k;
end
else if(j==1&&k==1)
begin
q<=~q;
qb<=~qb;
end
end
end
endmodul
MOORE OVERLAPPING:
module mooreover(x,j,k,clk,rst,q,qb,y);
input x,clk,rst;
input [2:0]j,k;
inout [2:0]q,qb;
output y;
wire w1,w2,w3,w4,w5,w6,w7,w8;
jkff g1(j[0],k[0],clk,rst,q[0],qb[0]);
jkff g2(j[1],k[1],clk,rst,q[1],qb[1]);
jkff g3(j[2],k[2],clk,rst,q[2],qb[2]);
and g4(j[0],q[0],qb[1],qb[2]);
and g5(w1,q[0],qb[1],qb[2]);
or g6(k[0],qb[0],w1);
and g7(w2,qb[0],q[2]);
STATE DIAGRAM:MEALY OVERLAPPING:

STATE TABLE:

PRESENT STATE NEXT STATE OUTPUT

X=0 X=1 X=0 X=1

S0 S0 S1 0 0

S1 S0 S2 0 0

S2 S3 S2 0 0

S3 S0 S1 0 1

TRANSITION TABLE:

PRESENT NEXT STATE OUTPUT

STATE
X=0 X=1 X=0 X=1

00 00 01 0 0

01 00 10 0 0

10 11 10 0 0

11 00 01 0 1
or g8(j[1],w2,w1);

and g9(w3,qb[0],qb[1],x);
or g10(k[1],w3,w1);
and g11(w4,qb[0],qb[2],x);
not g12(w5,x);
and g13(w6,qb[0],q[2],w5);
or g14(j[2],w4,w6)

or g15(k[2],w1,qb[0]);

and g17(w8,qb[0],q[1],qb[2],w5);
or g18(y,w7,w8);
endmodule
module jkff(j,k,clk,rst,q,qb);
input j,k,clk,rst;
output reg [3:0]q,qb;
wire j,k,clk,rst;
always@(posedgeclk)
begin
if(rst)
begin
q<=0;
qb<=1;
end
else begin
if(j!=k)
begin
q<=j;
qb<=k;
end
else if(j==1&&k==1)
begin
q<=~q;
qb<=~qb;
end
end
end
endmodule
EXCITATION TABLE:

PRESENT STATE NEXT STATE OUTPUT

Q0Q1 X=0 X=1 X=0 X=1
J0K0 J1K1 J0K0 J1K1
00 0X 0X 0 0
01 0X X1 0 0
10 X0 1X 0 0
11 X1 X1 0 1

K-MAP:

X Q1Q2

0 0 X X
0 1 X X
J1=XQ2

X Q1Q2

X X 1 0
X X 1 0
K1=Q2

X Q1Q2

0 X X 1
1 X X 0
J2=XQ1b+XbQ1

X Q1Q2

X 1 1 X
X 1 0 0
K2=Q1b+XbQ1

X Q1Q2

0 0 0 0
0 0 1 0
Y=XQ1Q2
LOGIC DIAGRAM:
MOORE NON OVERLAPPING:STATE DIAGRAM

STATE TABLE:

PRESENT NEXT STATE OUTPUT

STATE X=0 X=1 X=0 X=1
S0 S0 S1 0 0
S1 S0 S2 0 0
S2 S3 S2 0 0
S3 S0 S4 0 0
S4 S0 S1 1 1

TRANSITION TABLE:

PRESENT STATE NEXT STATE OUTPUT

Q1 Q2 Q3 X=0 X=1 X=0 X=1
0 0 0 000 001 0 0
0 0 1 000 010 0 0
0 1 0 011 010 0 0
0 1 1 000 100 0 0
1 0 0 000 001 1 1
EXCITATION TABLE:

PRESENT STATE NEXT STATE OUTPUT

Q1 Q2 Q3 X=0 X=1 X=0 X=1
JIKI J2K2 J3K3 JIKI J2K2 J3K3
0 0 0 0X 0X0X0X0X 1X 0 0
0 0 1 0X 0X X1 0X 1X X1 0 0
0 1 0 0X X0 1X 0X X0 0X 0 0
0 1 1 0X X1 X1 1X X1 X1 0 0
1 0 0 X1 0X 0X X1 0X 1X 1 1
K-MAP:

Q1Q2 Q3X Q1Q2 Q3X

X X X X
X 1 X X X

1 X
J1=Q1Q2bQ3b K1=Q1b+Q1Q2BQ3

Q1Q2/Q3X Q1Q2 Q3
X X X X 1
X 1 X X X

J2=Q1BQ3

Q1Q2 Q3 K2=Q1bQ2bX+Q1Q2bQ3b
X X 1
1 X x 1 1 x
x x x 1
X 1
1 x

J3=Q1Q2bQ3b+Q1bQ2bx+Q1bQ3Xb k3=Q1Q2bQ3b+Q1b

Q1Q2 Q3

1
Y=Q3(Q1Q2bX+Q1bQ2Xb)
LOGIC DIAGRAM:
MOORE OVERLAPPING: STATE DIAGRAM

STATE TABLE:

PRESENT STATE NEXT STATE OUTPUT

X=0 X=1 X=0 X=1
S0 S0 S1 0 0
S1 S0 S2 0 0
S2 S3 S2 0 0
S3 S0 S4 0 1
S4 S0 S2 0 0

TRANSITION TABLE:

PRESENT STATE NEXT STATE OUTPUT

X=0 X=1 X=0 X=1
000 000 001 0 0
001 000 010 0 0
010 011 010 0 0
011 000 100 0 1
100 000 010 0 0

EXCITATION TABLE:

PRESENT STATE NEXT STATE OUTPUT

X=0 X=1 X=0 X=1
000 0X 0X0X 0X0X 1X 0 0
001 0X 0X X1 0X 1X X1 0 0
010 0X X0 1X 0X X0 1X 0 0
011 0X X1 X1 1X X1 X1 0 0
100 X1 0X 0X X1 1X 0X 0 0
LOGIC DIAGRAM:
Sequence generator:
0 3 5 6 0 000 011 101 110 000

Transistion Table:
Present state Next state output

QA QB QC QA+ QB+ QC+ JA KA JB KB JC KC

0 0 0 0 1 1 O x 1 x 1 x
0 0 1 X X x x x x X x x
0 1 0 X X x x x x X x x
0 1 1 1 0 1 1 x x 1 x 0
1 0 0 X X x x x x X x x
1 0 1 1 1 0 x 0 1 X x 1
1 1 0 0 0 0 x 1 x 1 0 x
1 1 1 X X x x x x X x x

K-map:

QA QBQC QA QBQC
x x x x
0 X 1 x
x 0 x 1
x X X x
JA=QB KA=QB

QA QBQC QA QBQC
x x 1 x
1 X X x
x x x 1
x 1 X x
JB=A KB=1

QAQBQC QA QBQC
x x 0 X
1 X X x x 1 X X
x X 0 x
JC=QB KC=QB
SOURCE CODE:

module synch(d,clk,q,qb,rst);
input [0:3]d;
input clk,rst;
inout [0:3]q,qb;
wire [0:3]d;
dff u0(d[0],clk,rst,q[0],qb[0]);
dff u1(d[1],clk,rst,q[1],qb[1]);
dff u2(d[2],clk,rst,q[2],qb[2]);
dff u3(d[3],clk,rst,q[3],qb[3]);
and(w1,q[0],q[3]);
and(w2,q[0],q[1]);
and(w3,q[0],q[2]);
and(w4,qb[0],qb[1],qb[2],qb[3]);
or(d[0],w1,w2,w3,w4);
and(w5,q[1],q[3]);
and(w6,q[1],q[2]);
and(w7,qb[1],qb[2],qb[3]);
or(d[1],w5,w6,w7);
xnor(w8,q[2],q[3]);
or(d[2],w8,0);
or(d[3],qb[3],0);
endmodule

module dff(d,clk,rst,q,qb);
input d,rst,clk;
output qb;
output reg q;
assign qb=~q;
always@(posedge clk)
begin
if(rst==1'b1)
q=1'b0;
else
q=d;
end
endmodule
LOGIC DIAGRAM:
SYNCHRONOUS FSM:

TRANSITION:

PRESENT STATE
NEXT STATE FF INPUT

X + + Y
QA QB QA QB JA KA JB KB
0 0 0 0 0 0 0 X 0 X

0 0 1 0 1 0 0 X 1 X

0 1 0 1 0 0 1 X X 1

0 1 1 0 1 0 0 X X 0

1 0 0 1 0 0 X 0 0 X

1 0 1 1 1 0 X 0 1 X

1 1 0 1 1 0 X 0 X 0

1 1 1 0 0 1 X 1 X 1
LOGIC DIAGRAM:
RESULT:

Thus the design of sequence detector and sequence generator was successfully
implemented