DESIGNING

SYNCHRONOUS
COUNTERS
[9.5 FLOYD ]
++

Warning!! Important Topic

You may not find the details in the book
Question
 You have learned basic synchronous counters

 Now the question is

 Design of synchronous Counters, How?

 How about a machine that can give outputs in
the following sequence only
10, 01, 11 , 00 , 10, 01, 11 …
Designing a Synchronous Counter

 Develop a state diagram for a given sequence

 Develop a next-state table for a specified
counter sequence
 Create a flip-flop transition table

 Use the K-map method to derive the logic

requirements for a synchronous counter
 Implement a counter to produce a specified
sequence of states
Flip Flop State?

 Behavior of clocked sequential circuit can be determined

from inputs, outputs and FF state

Output equation y(t) = x(t)Q1(t)Q0(t)

Q0(t+1) = D0(t) = x(t)Q1(t)
State equation(s)
Q1(t+1) = D1(t) = x(t) + Q0(t)
 Flip Flop Input Equations
 Boolean expressions which indicate the input to
the flip flops.

DQ0 = x . Q1 Q0(t+1) = D0(t) = x(t)Q1(t)

DQ1 = x + Q0 Q1(t+1) = D1(t) = x(t) + Q0(t)
Output and State Equations

Next state dependents on previous/last state.

Output equation y(t) = x(t)Q1(t)Q0(t)

Q0(t+1) = D0(t) = x(t)Q1(t)
State equations
Q1(t+1) = D1(t) = x(t) + Q0(t)
State Table

 Sequence of outputs, inputs, and flip flop states

enumerated in state table
 Present state indicates current value of flip flops
 Next state indicates state after next rising clock edge
 Output is output value on current clock edge
Present Next State Output
State x=0 x=1 x=0 x=1
State Table 00 00 10 0 0
01 10 10 0 0
10 00 11 0 0
11 10 11 0 1
Q1(t) Q0(t) Q1(t+1) Q0(t+1)
State Table
 All possible input combinations enumerated
 All possible state combinations enumerated
 Separate columns for each output value.
 Sometimes easier to designate a symbol for each state.
Next State Output
Present
Let:
State x=0 x=1 x=0 x=1
s0 = 00 s0 s0 s2 0 0
s1 = 01 s1 s2 s2 0 0
s2 = 10 s2 s0 s3 0 0
s3 = 11
s3 s2 s3 0 1
State Diagram
 Circles indicate current state
 Arrows point to next state
 For x/y, x is input and y is
output

1/0 1/1
0/0
0/0 1/0
00 01 10 11
1/0 0/0
0/0
State Diagram (Example)
 Each state has two arrows leaving
 One for x = 0 and one for x = 1
 Unlimited arrows can enter a state
 Note use of state names in this example

 Easier to identify
1/0 1/1
0/0
0/0 1/0
S0 S1 S2 S3
1/0 0/0
0/0
Analysis with D Flip-Flops
 Identify flip flop input equations
 Identify output equation

Note: This circuit has no output

A is basically the state
State Equation (Example)

DQ0 = A (x y)
Q0(t+1) = D0(t) = A (x y)
 State Table (Example)
DQ0 = A (x y)
Q0(t+1) = D0(t) = A (x y)
A Input Input x XOR y A XOR w
x y =w = DQ

0 0 0 0 0
0 0 1 1 1
0 1 0 1 1
0 1 1 0 0

1 0 0 0 1
1 0 1 1 0
1 1 0 1 0
1 1 1 0 1
State Diagram (Example)

01,10
00,11
0 1
00,11
01,10
 Binary Counter (Example)
 A 3-bit Forward/Incremental Binary Counter
 No input (Just move to next state depending upon its
present/current state)
 No output (only Change of state)

 Only Clock 000 001 010 011

Current State Next State
000 001
001 010
Binary
Like
010 011 Odometer
011 100
100 101
101 110
110 111 111 110 101 100
111 000
Next Topics
 Sequential Circuit Analysis
 Sequential Circuit Design

 Designing with D Flip-Flops

 Designing with JK Flip-Flops

 Resources:

 Chapter #6, Mano Sections

◼ 6.4 Sequential Circuit Analysis
◼ 6.5 Sequential Circuit Design
Analysis of Sequential Circuits
 Earlier we learned how to analyze
combinational circuits
 Now extend to synchronous sequential

 We’ll use

 state tables and

 state diagrams
Review: Flip Flops Transition Table

D Flip Flop
(Transition Table)
D Q(t+1) Action
JK Flip Flop
0 0 Reset
(Transition Table)
1 1 Set
J K Q(t+1) Action
0 0 Q(t) No Change
T Flip Flop 0 1 0 Reset
(Transition Table) 1 0 1 Set
T Q(t+1) Action 1 1 Q(t)’ Complement
0 Q(t) No change
1 Q(t)’ Complement
Analysis of Sequential Circuits
 The behavior of a sequential circuit is
determined from the inputs, outputs and
present state of the circuit.
 The analysis of a sequential circuit consists of
obtaining a suitable description that
demonstrates the time sequence of inputs,
outputs and states.
Input Equations
 The input equations
 Imply the type of flip-flop from the letter symbols,
 Fully specify the combinational circuit that drives
the flip-flops
Input Equations
 Can describe inputs to FF with logic equations
J A = ( XB + Y C )

K A = (YB + C )
Another Example

DA = ( AX + BX )

DB = A X

Y = ( A + B) X
Time is Implied

 Note that last circuit

used the
 Previous state to
determine next state
 State and inputs to
determine output
 Synchronous circuit
 When are
transitions?
 (at Clock)
State Table
 Just truth table with state added
 A sequential circuit with `m’ FF and `n’ inputs
needs 2m+n rows in state table.
State Diagram

 An alternative
representation to
State Table

Input/Output
State Table vs. Diagram
 Same information
 Table is perhaps easier to fill in from
description
 Diagram is easier for understanding and
writing code
 Analysis for sequential circuits that employs

D- type flip flops is easy (i.e. next state values

are obtained directly from the input equations)
Analysis with JK Flip Flops
 For circuits with other types of flip flops such
as JK, the next state values are obtained by
following the two step procedure:
1) Obtain the binary values of each flip-flop input
equation in terms of the present state and input
variables.
2) Use the corresponding flip-flop characteristic to
determine the next state.
Analysis with JK Flip Flops (Input Eq.)

 JB = x’
 KB = A  x = A’x + Ax’

 JA = B

 KA = Bx’
JK Analysis- State Table
JK Flip Flop (Transition Table)
 JB = x’ J K Q(t+1) Action
0 0 Q(t) No Change
 KB = A  x = A’x + Ax’ 0 1 0 Reset
1 0 1 Set
1 1 Q(t)’ Complement
 JA = B
Present Next
 KA = Bx’
I/P FF “A” FF “B”
State State
A B x JA KA JB KB A B
0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0
0 1 0 1 1 1 0 1 1
0 1 1 1 0 0 1 1 0
1 0 0 0 0 1 1 1 1
1 0 1 0 0 0 0 1 0
1 1 0 1 1 1 1 0 0
1 1 1 1 0 0 0 1 1
JK Analysis State Diagram

Present Next
1 I/P FF “A” FF “B”
1 State State
A B x JA KA JB KB A B
00 0 11 0 0 0 0 0 1 0 0 1
0 0 1 0 0 0 1 0 0
0 1 0 1 1 1 0 1 1
0 0 0 0 1 1 1 0 0 1 1 0
1 0 0 0 0 1 1 1 1
01 10 1 0 1 0 0 0 0 1 0
1 1 1 0 1 1 1 1 0 0
1 1 1 1 1 0 0 0 1 1