Truth Tables, Characteristic Tables, Characteristic Equations and Excitation Tables of Different

Flip flops are given below: 1. SR Flip flop 2. JK Flip flop 3. D Flip flop 4. T Flip flop

SR Flipflop

Truth Table

S R Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Invalid inputs

Characteristic Table

S R Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 X

1 1 1 X

Characteristic Equation

Q(t+1) = R'(t)Q(t) + S(t) ; S(t)R(t) = 0

Excitation Table

Q(t) Q(t+1) S R

0 0 0 x

0 1 1 0

1 0 0 1

1 1 x 0
JK Flipflop

Truth Table

J K Q(t+1)

0 0 Q(t)

0 1 0

1 0 1

1 1 Q'(t)

Characteristic Table

J K Q(t) Q(t+1)

0 0 0 0

0 0 1 1

0 1 0 0

0 1 1 0

1 0 0 1

1 0 1 1

1 1 0 1

1 1 1 0

Characteristic Equation

Q(t+1) = K'(t)Q(t) + J(t)Q'(t)

Excitation Table

Q(t) Q(t+1) J K

0 0 0 x

0 1 1 x

1 0 x 1

1 1 x 0
D Flipflop

Truth Table

D Q(t+1)

0 0

1 1

Characteristic Table

D Q(t) Q(t+1)

0 0 0

0 1 0

1 0 1

1 1 1

Characteristic Equation

Q(t+1) = D(t)

Excitation Table

Q(t) Q(t+1) D

0 0 0

0 1 1

1 0 0

1 1 1
T Flipflop

Truth Table

T Q(t+1)

0 Q(t)

1 Q'(t)

Characteristic Table

T Q(t) Q(t+1)

0 0 0

0 1 1

1 0 1

1 1 0

Characteristic Equation

Q(t+1) = T'(t)Q(t) + T(t)Q'(t) = T(t) ⊕ Q(t)

Excitation Table

Q(t) Q(t+1) T

0 0 0

0 1 1

1 0 1

1 1 0
Difference between Serial Adder and Parallel Adder

1. Serial Adder:

A serial adder is used to add two binary numbers in serial form. The two binary numbers to be added
serially are stored in two shift registers. The circuit adds one pair at a time with the help of one full
adder. The carry output from the full adder is applied to a D flip-flop, the output of which is then used
as a carry input for the next pair of significant bits. However the sum bit S from the output of the full
adder can be transferred into a third shift register.

2. Parallel Adder :

A parallel adder is a combinational digital circuit that adds two binary numbers in parallel form. It
consists of full adders connected in cascade, with the output carry from each full adder connected to the
input carry of the next full adder.

Difference between Serial Adder and Parallel Adder:

Serial Adder Parallel Adder

It is used to add two binary It is used to add two binary numbers in

numbers in serial form. parallel form.

A serial adder uses shift A parallel adder uses registers with

registers. parallel loads.

It requires single full adder. It requires multiple full adders.

Carry flip-flop is used in Ripple carry adder is used in parallel

serial adder. adder.

Serial adder is a sequential

circuit. Parallel adder is a combinational circuit.

In serial adder, propagation In parallel adder, propagation delay is

delay is less. present from input carry to output carry.

Number of required full Number of required full adder is equal to

adder is fixed i.e. one. the number of bits in the binary number.
What Is Master Slave Flip Flop

Master Slave flip flop are the cascaded combination of two flip-flops among which the first is designated
as master flip-flop while the next is called slave flip-flop (Figure 1). Here the master flip-flop is triggered
by the external clock pulse train while the slave is activated at its inversion i.e. if the master is positive
edge-triggered, then the slave is negative-edge triggered and vice-versa. This means that the data enters
into the flip-flop at leading/trailing edge of the clock pulse while it is obtained at the output pins during
trailing/leading edge of the clock pulse. Hence a master-slave flip-flop completes its operation only after
the appearance of one full clock pulse for which they are also known as pulse-triggered flip-flops.

master slave flip flop

The internal structure of a master-slave JK flip-flop interms of NAND gates and an inverter (to
complement the clock signal) is shown in Figure 2. Here it is seen that the NAND gate 1 (N1) has three
inputs viz., external clock pulse (Clock), input J and output Q̅ ; while the NAND gate 2 (N2) has external
clock pulse (Clock), input K and output Q as its inputs.

Further the outputs of N1 and N2 gates are connected as the inputs for the criss-cross connected gates N3
and N4. These four gates together (N1, N2, N3 and N4) form the master-part of the flip-flop while a
similar arrangement of the other four gates N5, N6, N7 and N8 form the slave-part of it.

master slave flip flop

From figure it is also evident that the slave is driven by the outputs of the master (M1 and M2), which is
in accordance with its name master-slave flip-flop. Further the master is active during the positive edge of
the clock due to which M1 and M2 change their states; depending on the values of J and K. However at
this instant the outputs of the overall system (master-slave JK flip-flop) remains unchanged as the slave
will be inactive due to positive-edge of the clock pulse. Similar to this, the slave decides on its outputs Q
and Q̅ depending on its inputs M1 and M2, during the negative edge of the clock during which the master
will be inactive.

The truth table corresponding to the working of the flip-flop shown in Figure 2 is given by Table I. Here
it is seen that the outputs at the master-part of the flip-flop (data enclosed in red boxes) appear during the
positive-edge of the clock (red arrow). However at this instant the slave-outputs remain latched or
unchanged. The same data is transferred to the output pins of the master-slave flip-flop (data enclosed in
blue boxes) by the slave during the negative edge of the clock pulse (blue arrow). The same principle is
further emphasized in the timing diagram of master-slave flip-flop shown by Figure 3. Here the green
arrows are used to indicate that the slave-output is nothing but the master-output delayed by half-a-clock
cycle.

Moreover it is to be noted that the working of any other type of master-slave flip-flop is analogous to that
of the master slave JK flip-flop explained here.

Master Slave flip flop are the cascaded combination of two flip-flops among
which the first is designated as master flip-flop while the next is called slave
flip-flop (Figure 1). Here the master flip-flop is triggered by the external clock
pulse train while the slave is activated at its inversion i.e. if the master is
positive edge-triggered, then the slave is negative-edge triggered and vice-
versa. This means that the data enters into the flip-flop at leading/trailing edge
of the clock pulse while it is obtained at the output pins during
trailing/leading edge of the clock pulse. Hence a master-slave flip-flop
completes its operation only after the appearance of one full clock pulse for
which they are also known as pulse-triggered flip-flops.

The internal structure of a master-slave JK flip-flop interms of NAND gates

and an inverter (to complement the clock signal) is shown in Figure 2. Here it
is seen that the NAND gate 1 (N1) has three inputs viz., external clock pulse
(Clock), input J and output Q̅; while the NAND gate 2 (N2) has external clock
pulse (Clock), input K and output Q as its inputs.
Further the outputs of N1 and N2 gates are connected as the inputs for the
criss-cross connected gates N3 and N4. These four gates together (N1, N2, N3
and N4) form the master-part of the flip-flop while a similar arrangement of
the other four gates N5, N6, N7 and N8 form the slave-part of it.

From figure it is also evident that the slave is driven by the outputs of the
master (M1 and M2), which is in accordance with its name master-slave flip-
flop. Further the master is active during the positive edge of the clock due to
which M1 and M2 change their states; depending on the values of J and K.
However at this instant the outputs of the overall system (master-slave JK
 flip-flop) remains unchanged as the slave will be inactive due to positive-edge
of the clock pulse. Similar to this, the slave decides on its outputs Q and Q̅
depending on its inputs M1 and M2, during the negative edge of the clock
during which the master will be inactive.
The truth table corresponding to the working of the flip-flop shown in Figure
2 is given by Table I. Here it is seen that the outputs at the master-part of the
flip-flop (data enclosed in red boxes) appear during the positive-edge of the
clock (red arrow). However at this instant the slave-outputs remain latched or
unchanged. The same data is transferred to the output pins of the master-
slave flip-flop (data enclosed in blue boxes) by the slave during the negative
edge of the clock pulse (blue arrow). The same principle is further
emphasized in the timing diagram of master-slave flip-flop shown by Figure
3. Here the green arrows are used to indicate that the slave-output is nothing
but the master-output delayed by half-a-clock cycle.
Moreover it is to be noted that the working of any other type of master-slave
flip-flop is analogous to that of the master slave JK flip-flop explained here.

 JK Flip Flop: What is it? (Truth Table &…

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