FSM Problem Solution

Arghya Kamal Dey

193070053

Question:
Implement an FSM with the following specification:
• The set of input symbols is Σ = {a, b}.
• The set of output symbols is Λ = {Y, N }.
The behaviour of the FSM is as follows:
• The FSM outputs a Y at time instant k only if the last 4 inputs were
either
abab
baba
(that is, either x(k) = a, x(k − 1) = b, x(k − 2) = a, x(k − 3) = b or x(k) = b, x(k − 1) = a, x(k − 2) = b,
x(k − 3) = a). Otherwise the FSM outputs N .

Suppose you are given the following building blocks:

• Inverters, NAND2, NOR2 gates each with a delay of 2 units.
• D-flipflops with clock → q delay of 3 units, set-up time of 2 units and hold-time of 2 units.
1. Design an abstract Mealy machine (identify a potential set of states and next-state, output
functions) which implements the required behaviour.
2. Minimize the set of states by finding compatible subsets of states.
3. Encode the input, output and state symbols using binary encoding.
• Try two state encodings: the one-hot encoding and a compact encoding using log 2 |Q| state
variables.
4. Complete the logic network for the FSM based on your encodings. Don’t forget to add the reset
signal. You may assume that the output is a dont-care when the reset signal is applied.
5. Confirm that your implementations are correct. Check the following test-case
k0 123456789
x reset a b b a b a b a a
y - N N N N NYYYN
6. Characterize the timing of your FSM implementations (find the minimum
and maximum values of the input to flop, flop to flop, flop to output and
input to output delays).

Solution:
1. The abstract Mealy Machine after minimization looks like following:

Reset
RST

b/N a/N

b/N a/N
Sb Sa

b/N a/N
a/N b/N
b/N a/N

Sba Sab

b/N a/N
a/Y

Sbab Saba

b/Y
Fig. 1: State Diagram for the Mealy Machine

3. Compact encoding is used here using log2|Q| no of states.

• For input reset and x variables are used
 variables
reset x
symbol
sreset 1 don’t care
a 0 0
b 0 1

• The output symbol is encoded in 1 bit

symbol variable(y)
Y 1
N 0

• The states are encoded in three variables

State S2 S1 S0
RST 0 0 0
Sa 0 0 1
Sb 0 1 0
Sab 0 1 1
Sba 1 0 0
Saba 1 0 1
Sbab 1 1 0
4.
The present-state next-state table is given below:
input Present States Output Next-State

x S2 S1 S0 y S2 S1 S0
0 0 0 0 0 0 0 1
0 0 0 1 0 0 0 1
0 0 1 0 0 1 0 0
0 0 1 1 0 1 0 1
0 1 0 0 0 0 0 1
0 1 0 1 0 0 0 1
0 1 1 0 1 1 0 1
0 1 1 1 d d d d
1 0 0 0 0 0 1 0
1 0 0 1 0 0 1 1
1 0 1 0 0 0 1 0
1 0 1 1 0 0 1 0
1 1 0 0 0 1 1 0
1 1 0 1 1 1 1 0
1 1 1 0 0 0 1 0
1 1 1 1 d d d d

Using K-map for minimization of Output logic in terms of input and present states.
S1S0
xS2

d 1
1 d

Output y= x S2 S 0 + x̄ S2 S 1

Next state nS2 is found from the following K-map

S1S0
xS2

1 1
d 1
1 1 d
Therefore nS2 can be written as nS2 = reset
¯ ( x̄ S1 + x S2 S¯1)

Similarly,
S1S0
xS2

d
1 1 d 1
1 1 1 1

nS1= reset
¯ x

S1S0
xS2

1 1 1
1 1 d 1
D
1

nS0= reset
¯ ( S¯2 S̄1 S 0 + x̄ S2 + x̄ S̄ 1+ x̄ S 0 )
5.

The timing of the FSM implementation is given as follows:

Fig.: Logic circuit for Output

• The input-to-output delay is 6 units.

• The flop-to-output delay is 9 units.
 Logic Circuit for nS2

• The maximum flop-to-flop delay for S2 is 17 units.

• The minimum flop-to-flop delay for S2 is 11 units.
• The input-to-flop delay for S2 is 12 units.

Logic circuit for nS1

• The input-to-flop delay for S1 is 4 units.

Logic circuit for nS0

• The maximum flop-to-flop delay is 15 units.

• The minimum flop-to-flop delay is 13 units
• The input-to-flop delay is 10 units.
 • Therefore the maximum flop-to-flop delay in the circuit is 17 units.
• The minimum flop-to-flop delay is 11 units.

Tclock has to be greater than 19 units, as setup time is 2 units.

Minimum flop-to-flop delay is 11 units which is greater than 2 units of hold time.
Therefore the circuit will work correctly.

Solution 2:
3. Here one-hot encoding is used for the states
• For input reset and x variables are used
variables
reset x
symbol
sreset 1 don’t care
a 0 0
b 0 1
• The output symbol is encoded in 2 bit
symbol variable(y)
Y 1
N 0

• The states are encoded in three variables

State S6 S5 S4 S3 S2 S1 S0
RST 0 0 0 0 0 0 1
Sa 0 0 0 0 0 1 0
Sb 0 0 0 0 1 0 0
Sab 0 0 0 1 0 0 0
Sba 0 0 1 0 0 0 0
Saba 0 1 0 0 0 0 0
Sbab 1 0 0 0 0 0 0
4. From the FSM the output logic
y= S 6 x̄+ S5 x
 The State variale logics can also be found similarly.
S 0=Reset

S 1= Reset
¯ (( S 0+ S 1+ S 4 + S5 ) x̄ )

S 2= Reset
¯ ( x (S 0 +S 2 +S 3 +S 6 ))

S 3= Reset
¯ (S1 x )

S 4 = Reset(S
¯ 2 x̄)

S 5= Reset
¯ ( x̄ (S 3 +S 6 ))

S 6= Reset
¯ (x (S4 + S 5))

There are 7 flip-flops here.

Logic circuit for output

• The maximum input-to-output delay is 6 units.
• The minimum input-to-output delay is 4 units.
• The flop-to-output delay is 7 units.
• For S0, the input-to-flop delay is 0 unit.
• For S1, the logic circuit is

• The input-to-flop delay is 6 units.

• The flop-to-flop delay is 15 units.
• For S2, the logic circuit is

• The input-to-flop delay is 8 units.

• The flop-to-flop delay is 15 units.
• For S2, the logic circuit is

• The input-to-flop delay is 4 units.

• The flop-to-flop delay is 7 units.
• For S4, the logic circuit is,

• The input-to-flop delay is 6 units.

• The maximum flop-to-flop delay is 9 units.
• The minimum flop-to-flop delay is 7 units.
• For S5, the logic circuit is,

• The input-to-flop delay is 6 units.

• The flop-to-flop delay is 11 units.
• For S6, the logic circuit is,

• The input-to-flop delay is 8 units.

• The flop-to-flop delay is 11 units.

• The maximum flop-to-flop delay is 15 units

• The minimum flop-to-flop delay is 7 units.
• The Tclk has to be greater than 15 units.
• The minimum flop-to-flop delay is 7 units which is greater than hold time. So the circuit
works correctly.