EE 671: VLSI DESIGN

Assignment-3
Name: ARGHYA KAMAL DEY Roll No. :193070053

Q–1
a) Dadda Multiplier for unsigned 16 x 16 multiplier with a Brent-Kung
Adder for final stage is made using the dot diagram in fig. 1.

Fig. 1: Dadda multiplier for unsigned 16 X 16 bits

Fig. 2: Waveform for multiplier without delays in Synthesizable code
Fig. 3: Critical path in the dadda multiplier
b) The delays of the each component was back-annotated later.
There are multiple critical path in the dadda multiplier but the Brent- Kung adder stage
the latest bit to arrive is b31 or the MSB.
The maximum time taken for the multiplication to complete is 5.7 ns.