Virtual Circuit (VC) Representation in the AHIR

flow

Madhav P. Desai
Department of Electrical Engineering
IIT Bombay, Mumbai

November 16, 2020

Overview

I An intermediate step in the C/Aa to VHDL transformation.

I Structural description of the sytem.
I Modules.
I Pipes.
I Memory subsystems.
I Modules.
I Control-path, data-path, memory subsystems.
An example

I Two modules foo and bar.

I foo calls bar.
I foo and bar exchange information through two pipes foo bar
and bar foo.
I foo and bar exchange information through two storage arrays
mA and mB.
I Take a look.
Structural view
AHIR System VC description
memory memory
pipe
foo_bar
mA mB

Pipe bar_foo

module foo module bar

DP IO in store store
Load mA IO in DP
mA mB
IO out Load mB IO out
~
+ + call bar
links links
CP CP

Control Petrinet Control Petrinet

Figure: Structure in a VC representation

Take a look at the VC file

I Pipe declarations.
I Constant declarations.
I Memory space declarations: collection of storage variables.
I Module descriptions.
Module description in the VC file

$module [bar]
{
$CP
{
.. petri-net ..
}
$DP
{
.. graph of data-path operators ..
}
... link descriptons ...
}
Control path description in the VC file

I Block structured.
I Series block ;; contains only transitions.
I Branch block ¡¿ contains places and transitions.
I Parallel block ——
I Fork block :: contains only transitions.
I Pipelined fork block :—: contains a pipeline control scheme.
I Loop block ¡o¿ models a do-while loop.
Control path description in the VC file

I Transition declarations.
I Place declarations.
I Dependencies between transitions.
I Dependencies between places and transitions.
I Special structures:
I $transition merge, $phisequencer, $terminate.
I $bind
.
Control path description in the VC file

I Each control block has a default entry transition $entry and a

default exit transition $exit.
I Transitions are mapped to data-path operators using the links
after the data path description.
I Transitions are identified by a hierarchical name while
specifying the links.
Data path description in the VC file

I Wire declarations $W [wname]

I Constant wire declarations.
I Intermediate wire declarations. For example q := ((a + b) + c)
has an intermediate wire to store the result of (a + b).
I Operators
I unary, binary, ternary, output port, input port, load, store, call,
phi.
Data path operators in the VC file

I A data path operator is marked as $flowthrough if it is a

combinational operator.
I The input and output buffering for data path operators is also
specified in the data path description.
Links in the module description in the VC file

I Each data path operator has two pairs of request/ack

transitions for sample and update control.
I Exceptions: output ports have only sample req/ack
transitions, and input ports have only update req/ack
transitions.
I The control path to data path operator connections are
specified in the links after the data path description.
I The links are specified for each data path operator of interest
in the data path.
Things not specified in the VC file

I Operator sharing.
I Arbitration.
I Connection details.
I The vc2vhdl utility
I Simplifies the control path.
I Determines operator sharing.
I Generates the VHDL structural netlist together with arbiters,
pipes and memory instantiation.