BUS

Typical I/O Organization

PROCESSOR MEMORY

SYSTEM BUS

I/O I/O I/O o o o

I/O
INTERFACE INTERFACE INTERFACE INTERFACE

I/O
I/O DEV
I/O
DEV DEV I/O I/O
DEV DEV
I/O I/O
DEV DEV
I/O BUS I/O I/O
DEV DEV
I/O I/O I/O
DEV DEV DEV

The system bus consists of a common set of signal lines shared by the
interfaces for exchange of data and control information. These signal lines are:
• Address Lines,
• Data lines,
• Control lines.
 BUS
Shared set of signal lines for exchange of data
between the Processor, Memory and the I/O Device
Interfaces:
▪ Address Lines
▪ Data Lines
▪ Control Lines
• Command lines
• Data Transfer Handshake lines
• Interrupt Control Lines
• DMA Control lines
• Clock
• Reset
• Power Supply & Ground
• Utility Signal lines
 Signal Lines on the Bus
❖ Party lines:
• Signal lines driven by Tristate Buffers
• Used for signals those are driven by only one device at-a-time.
e.g. Data, Address, Command lines etc.

❖ Wired-OR
• Signal lines driven by Open Collector/ Open Drain drivers
• Used for signals that may be asserted by multiple devices
simultaneously.
e.g. Interrupt Request, Bus Request etc.

❖ Daisy Chained
• Signal lines propagate through the interfaces.
• Used for assigning priority to the interfaces.
- Electrically closer interfaces get higher priority
e.g. Interrupt Acknowledgement, Bus Grant etc.
 Party Line Driver

Truth Table
Enable Data Output
1 0 0
1 1 1
0 0 Hi-Z
0 1 Hi-Z
 Bus Lines
Enable1
Party
Lines
Data
Register

Interface1

Enable2

Data
Register

Interface2
 Bus
R1in Enable1 Lines

Clock

Enable2

R2in
 ▪ These are Open Collector (OC)/ Open Drain (OD)
Wired-OR signal lines to provide Active Low OR effect to the
signals connected to the bus line.
Signal Line ▪ The output circuit of the bus driver devices for the
signal line is kept open.
Vcc ▪ The resistor Rc/ Rd connecting the collector/ drain
to the power supply of the BJT/ FET of the output
stage of the driver is not placed in the driver.
▪ A Rc / Rd is placed in the bus which is shared by
the drivers of all the interfaces sharing the signal
line.
▪ A wired-OR signal line is always Active Low.

IRQ

Interface Circuit Interface Circuit Interface Circuit

 Daisy Chain

Signal

Interface1 Interface2 Interface3

Signalin Signalout

Inhibit
Questions ?
Bus Arbitration

❖ Centralized
• A central arbiter control the bus arbitration/
allocation process.

❖ Distributed
• Logic circuits distributed in the interfaces
resolve the bus allocation process.
Centralized Bus Arbitration
BRQk# are k OC Bus
BRQ1# Request signal lines.
Bus BRQ2# Each I/O interface is
Arbitration BBSY# hooked to one of
Unit BGNT# these k lines for
Interface Interface Interface Interface raising its Bus
C D A B Requests.
An interface hooked
to a Lines with
Allocation Process Timing Diagram: higher k value get
higher priority in
BRQ1# REQ-A REQ-B bus allocation.

BRQ2# REQ-C BBSY#: Bus Busy

signal line (Binary)
BBSY# A Master C Master B Master
asserted by the Bus
Master
BGNT#

• BGNT#: Binary Bus Grant signal line driven by the Bus

Arbitration Unit. It is Daisy Chained through the I/O interfaces
Questions ?
 Distributed Bus Arbitration
Vcc All the signal lines on the bus are Open Collector and hence ‘0’ prevails on
the bus line. However, as far as the I/O interface is concerned, a ‘1’ prevails,
as the output of the interface is inverted before placing on the bus.

ARB0#

ARB1#
ARB2#
Start Arbitration#
BBSY#

1 1 0 1 1 0
1 0 x 1 1 1 0

I/O Interface Circuit 1

I/O Interface Circuit 2

It means that if one interface outputs a ‘1’ and

another outputs ‘0’, the outputs will be ‘1’.
 Distributed Bus Arbitration
▪ Each interface is assigned a priority code.
▪ Interface having a code with higher value has higher priority.
▪ Arbitration starts with the assertion of the Start Arbitration#
signal by an interface.
▪ When an interface acquires the bus mastership it asserts the
BBSY# (Bus Busy) signal.
▪ An interfaces wanting bus mastership will first check if the BBSY#
signal is in asserted state. If, will assert the Start Arbitration# and
place its priority code on the ARB lines to acquire the bus
mastership.
▪ However, it is possible that more than one interface may be
waiting to become the bus master while another interface is
holding the bus mastership. All these interfaces contending for
the mastership will assert the Start Arbitration# signal as soon as
the BBSY# signal is de-asserted. This contention is resolved as
follows:
 Distributed Bus Arbitration
▪ The contending interfaces will place their priority codes one bit
at a time in the order of the MS bit being placed first and the LS
bit last.
▪ After placing a bit on the corresponding ARB# line the interface
will read back the ARB# line and check if it matches with the
asserted value. If it matches the interface will proceed to place
the next bit of the priority code, else it will withdraw from the
contention.
▪ After placing of the last bit of the priority code only one
interface will find the read back value to be same as that of its
priority code and that interface becomes the Bus Master and it
asserts the BBSY# signal.
▪ The Bus Master after completion of its use of the bus release it
by de-asserting the BBSY# signal.
Questions ?
 Data Transfer Protocols

• Steps followed in the process of transfer of data between

processor/ interface(I/O) and memory/ interface(I/O)
• Timings of the control/ command signals,
• Timings of placing of address, data on the bus and clocking
in of data

• Parallel / Serial Data Transfer

 Data Transfer Protocols

Synchronous/ Asynchronous Data Transfer

Synchronous Data Transfer:

• Timings of events on the bus are synchronized with a bus
clock.

Asynchronous Data Transfer:

• Timings of events on the bus are not synchronized with a
bus clock.
 Synchronous Parallel Data Transfer

• Timings of the events are determined by a clock.

Bus Clock

Address

RD/WR

Data

t0 t1 t2 t3 t4
 Asynchronous Parallel Data Transfer
Strobe
1. Strobing Initiator RD/WR’ Responder
Address
Operation: Device Device
Data
• Strobe issued
by the Master;
duration is
Shortcomings:
fixed. Strobe • Strobe duration is
decided by the
• Address and
slowest I/O
Command are
RD/WR’ interface. Hence,
issued at the
the bus speed is
leading edge of
Address limited to the
Strobe.
speed of the
• The Slave slowest device
device decodes
Data • If the addressed
the address &
I/O interface is
places the Data
absent or faulty
on bus within t0 t1 t2
the data transfer
the strobe.
will be incorrect.
• The trailing edge of Strobe clocks in the Data in the Master.
• The Address, Command and Data are removed after the trailing
edge of Strobe.
 Asynchronous Parallel Data Transfer
2. Handshaking

Master Ready/ Sync/ Init

Master Slave
Slave Ready/ Ack
Device Device
RD/WR’

Address

Data

Sync- Synchronize
Init- Initialize
Ack- Acknowledgement
RD- Read
WR- Write
 Asynchronous Parallel Data Transfer
• Overcomes the
2. Handshaking • A Timeout
problems in mechanism is
Strobing by
- An Input (Read) Operation) introduced to
introducing the take care of
Slave Ready (ACK) scenarios of
signal Master the Slave being
Ready absent or
• The Master Ready (SYNC/ INIT)
signal does the job faulty.
of Strobe RD/WR’ • At Timeout
• The operation interrupt is
terminates only on Address generated in
receipt of ACK the Master if
from the Slave Slave
an ACK is not
device. Ready received within
(ACK) a set time.
• Duration of the
operation can vary Data
depending on how
soon the Slave can
issues ACK. t0 t1 t2 t3 t4 t5
Asynchronous Parallel Data Transfer
2. Handshaking
- An Output (Write) Operation

Master
Ready
(Sync/Init)

RD/WR

Address

Slave
Ready
(Ack)
Data

t0 t1 t2 t3 t4 t5
Questions ?
 Asynchronous Serial Data Transfer Protocols

• In serial data transfer it is not economical to have additional

pair of signal lines to transmit the clock signal.
• The transmitter and the receiver both have their own clocks.
• It is necessary to ensure that the receiver clock is
synchronized with the transmitter clock.
• Problem arises due to the clocks being not 100% accurate.
Clocks with accuracies of up to 99.99% or even better are
available. But that is not good enough.
• Example protocol: RS 232
 Asynchronous Serial Data Transfer Protocols
• In RS232 the clocks are assumed to be accurate enough for
the duration of transmission of one character (i.e. 8 bits).
• Therefore, transmission is done one character (8 bits) at a time.
• The receiver clock is synchronized at the start of receiving every
character.
• For this purpose, a negative transition is introduced at the start of
every character transmission. This is done by having a Start bit (low)
after the Stop bit (high) of the previous transmission.
• The receiver clock corrects itself, in case of any drift, at this falling
edge.

1 or more
Stop Bits
Start Bit Data Bits Parity Start Data Bits
Bit Bit
Next Character
One Character Transmission Transmission
Questions ?
 Synchronous Serial Data Transfer Protocols

• Synchronous serial data transfers are carried out in blocks

in the form of frames.

• Typical format of a frame:

Frame Address(es) Data Error Check Frame

Delimiter Bits Delimiter

• Example Protocols: USB, HDLC

• To ensure synchronization the bits are

encoded to provide self-clocking.
Questions ?
Example Buses
Variations in Buses
• System Bus
• Mostly Backplane buses (Copper lines printed on PCBs)
• I/O Bus: Parallel, Serial
• Mostly Cable based

• Synchronous/ Asynchronous
• Time Multiplexed/ Dedicated
• Bus Width (8/16/32/64 bit)
• Control: Centralized/ Distributed
Example System Buses
• Unibus
• Multibus
• S-100
• VME
• Nu Bus
• Future Bus
• Q Bus
• Fast Bus
• HP Precision Bus
• MCA (Micro Channel Architecture)
• TURBOchannel
• STD Bus
• PC Bus
• XT Bus
• ISA (Industry Standard Architecture) Bus
• EISA (Extended ISA) Bus
• PCI (Peripheral Component Interconnect) Bus etc.
Example I/O Buses

Parallel Buses:
• Centronics/ IEEE-1284 – Parallel Printer Interface

• HPIB/ GPIB/ IEEE-488 (HP I/O Bus/ General purpose I/O Bus)
– Instruments Bus

• SCSI (Small Computer System Interface)

– Used in servers for highspeed I/O devices

• PATA (Parallel AT Attachment)

– Used in desktops for highspeed I/O devices
 Example I/O Buses
Serial Buses:
• RS-232
• RS-422
• RS-423
• RS-485
• USB (Universal Serial Bus) - For connecting peripherals to computers
• Fibre Channel - High-speed, for connecting computers to mass storage devices.
• ARINC 818 - Avionics Digital Video Bus
• FireWire/ IEEE 1394)
• MIDI (Musical Instruments Digital Interface) – Communication with electronic
musical instruments
• Serial ATA (SATA) – High speed mass storage devices
• SpaceWire (IEEE 1355) - Spacecraft communication network
• I²C (Inter-Integrated Circuit Communication)
• SPI (Serial Peripheral Interface) – For short distance communication
Questions ?
PCI (Peripheral Component Interconnect) Bus

- Synchronous Bus
- 32/ 64-bit wide
- Data Rates:
133 MBPS (32-bit at 33 MHz)
266 MBPS (32-bit at 66 MHz or 64-bit at 33 MHz)
533 MBPS(64-bit at 66 MHz)
- Bus Lines Time Multiplexed

- Provides for three address spaces:

- Memory space,
- I/O space,
- Configuration space

Refer to: Computer Organization: Hamacher, Vranesic, Zaky

PCI Bus
Important Signals
–CLK : A 33 MHz or 66 MHz Clock.

–FRAME# : Issued by the Initiator to indicate the duration of the transfer.

–AD : Multiplexed 32/64 Address/ Data lines.

–C/BE# : 4 Command/Byte Enable Lines (8 for 64-bit bus).

–IRDY# : Initiator Ready Signal.

–TRDY# : Target Ready Signal.

–DEVSEL# : A response from the device interface indicating that it has

recognized its address and is ready for data transfer transaction.

–IDSEL# : Initialization Device Select. Used during system Booting-up. This

signal line is connected to one of the AD11-AD31 lines in the
interface to select it for configuration.
PCI Bus
Category wise Signal Pins:
System Pins : Clock (CLK), Reset (RST#)

Address & Data : Time multiplexed 32/64-bit wide(AD), C/BE#, PAR

Interface Control : FRAME#, IRDY#, TRDY#, STOP#, LOCK#, IDSEL#,

DEVSEL#

Arbitration Pins : REQ#, GNT#

Interrupt Pins : INTA#, INTB#, INTC#, INTD#

Error Reporting : PERR#, SERR#

Cache Support : SBO#, SDONE

JTAG/Boundary Scan: TCK, TDI, TDO, TMS, TRST#

 PCI Commands
0000 Interrupt Acknowledge : This is a special form of read cycle implicitly
addressed to the interrupting device which returns an interrupt vector.
0001 Special Cycle : This cycle is a special broadcast write of system events
that PCI card may be interested in.
0010 I/O Read : This performs a read from I/O space.
0011 I/O Write: This performs a write to I/O space.
010x Reserved
0110 Memory Read: This performs a read cycle from memory space.
0111 Memory Write
100x Reserved
1010 Configuration Read : This is similar to an I/O read but reads from PCI
configuration space. A device must respond only if the low 11 bits of the
address specify a function and register that it implements, and if the
special IDSEL signal is asserted. It must ignore the high 21 bits.
1011 Configuration Write
 PCI Commands
1100 Memory Read Multiple : This command is identical to a generic
memory read but includes the hint that a long-read burst will
continue.

1101 Dual Address Cycle : When accessing a memory address that requires
more than 32 bits to represent, the address phase begins with this
command and the low 32 bits of the address, followed by a second
cycle with the actual command and the high 32 bits of the address.

1110 Memory Read Line : This command is identical to a generic memory

read but includes the hint that the read will continue to the end of
the cache line.

1111 Memory Write and Invalidate : This command is identical to a generic

memory write but comes with the guarantee that one or more
whole cache lines will be written, with all byte selects enabled. This
is an optimization for write-back caches.
PCI Read Operation:

Clock

Frame#

AD A D D D D

C/BE# C BE#

IRDY#

TRDY#

DEVSEL#
PCI Read Operation (with use of IRDY#, TRDY#):

Clock

Frame#

AD A D D D D

C/BE# C BE#

IRDY#

TRDY#

DEVSEL#
Questions ?
 Universal Serial Bus (USB)

➢ I/O devices away from the computer

▪ Leads to high data skew in case of parallel bus
➢ Low cost, Flexibility, High data transfer rate
➢ Supports 3 different speeds:
▪ 1.5 mbps - Low Speed (LS)
▪ 12 mbps - Full Speed (FS)
▪ 480 mbps – High Speed (HS)
➢ Supports Plug-and-Play
Universal Serial Bus (USB)
Electrical Characteristics:
❑ 4 wires
o 2 wires used to carry power, +5V and GND.
o 2 wires used for data
▪ Different signaling schemes are used for
different speeds
• LS: 1s and 0s are transmitted by sending High
or Low voltage state on one or the other wire.
• HS: Differential transmission is used.
 USB Bus Structure
Tree structure to
o Each hub has a number of
accommodate HOST ports where I/O devices or
large number of Root other hubs may be
Hub
devices that can connected.
be added or o A hub copies a message
that it receives from up-
removed at any Hub
Hub
stream connection to its
time. down-stream ports.
▪ A message
I/O
Hub sent by the
I/O I/O I/O
Device Device Device Device host is
broadcast
I/O I/O I/O to all I/O
Device Device Device devices.

➢ Each node of the tree has a device called HUB.

o HUB acts as an intermediate control point between the host and the
I/O device.
o Root of the tree is the ROOT-HUB.
o The Leaves of the tree are the I/O devices, called FUNCTIONS.
USB Bus Structure
▪ A message sent by the host is broadcast to all I/O devices.
o Only the addressed device responds to a message.
▪ A message from an I/O device is sent up stream towards the
root of the tree and is not seen by the other devices.
▪ Uses Polling:
o A device may send a message only in response to a poll
message from the host.
▪ Split-bus Operation:
o Devices with HS and FS/LS may share a hub.
o This allows USB to support devices of different speeds
simultaneously.
USB Bus Structure
Addressing:
o The root hub is attached to the system bus.
o The host communicate with the individual devices by
sending packets of information through the root hub.
o Each device (Hub/ I/O device) on the USB is assigned a
7-bit address local to the USB tree.
o Locations in a device such as Status, Control, Data
registers are called the End Points.
▪ End points are identified by 4-bit numbers.
▪ Each 4-bit number identifies a pair of end-points,
one for input and the other for output.
▪ There can be up to 16 pairs of end-points.
USB Bus Structure
Plug & Play:
o When a device is connected or it is powered on,
it has the address ‘0’. The hub records the new
device as part of its status.
o Periodically, the host polls each hub to collect
status information and learns about the new
devices connected or the ones disconnected.
o On detection of a new device the host sends a
sequence of commands
▪ to reset the hub port,
▪ to read the capabilities information of the
device,
▪ to configure the device,
▪ to assign the device a unique USB address.
USB The Protocol:
o All information transferred in the form of packets.
o Control Packets perform control functions
o Addressing
o Initiation of data transfer
o Acknowledging data received correctly
o Indicating an error.
o Data packets carry information to or from a device.

Packet Formats: Data Packet

8 0 to 8192 16
Token Packet
8 7 4 5 PID DATA CRC16
PID Address EndP CRC

PID (Packet Id) Field

PID0 PID1 PID2 PID3 PID0 PID1 PID2 PID3
USB Output Data Transfer:
Host Hub I/O Dev
The Protocol:
o All information transferred
Token in the form of packets.
Data0 o Control (Token) Packets
Ack perform control functions
Token o Addressing
Data0
o Initiation of data transfer
o Acknowledging data
Ack received correctly
Token
o Indicating an error.
Data1
o Data packets carry
Ack information to or from a
Token
Data1
device.

Ack
Questions ?
Thank You