Input / Output Organization

Introduction
 CPU

INPUT MEMORY OUTPUT

Input Devices: Keyboard, Mouse, Track ball, Camera,

Microphone, Sensors, Communication link,
Storage device etc. etc.
Output Devices: LCD display, Printer, Plotter, Loud speaker,
Transducers, Communication link, Storage device
etc. etc.
 Some of the ways in which the I/O
devices differ are-
1. Speed of Data Transfer: Ranging from a few bytes per minute in
telemetry devices or a few bytes per second in a keyboard to some gigabits
per second for data communication devices or high-speed storage devices.
2. Interface: Serial/ parallel:
Single bit at-a-time or Multiple bits at-a-time.
3. Connector: Type of connector
4. Protocol: Steps involved in the transaction of data.
5. Unit of data transferred:
Character/ byte:
Data bits transferred grouped in units of bytes.
Block:
Data bits transferred grouped in hundreds of thousands of bits.
 Typical I/O Organization
PROCESSOR MEMORY

SYSTEM BUS

I/O I/O I/O I/O

o o o
INTERFACE INTERFACE INTERFACE INTERFACE

I/O
I/O DEV
I/O
DEV DEV I/O I/O
DEV DEV
I/O I/O
DEV DEV
I/O BUS I/O I/O
DEV DEV
I/O I/O I/O
DEV DEV DEV

The system bus consists of a common set • Address Lines,

of signal lines shared by the interfaces for • Data lines,
exchange of data and control information. • Control signal lines.
These signal lines are:
The I/O Interface Consists of-
1. System Bus Interface:
The system bus interface consists of a set of registers and a decoder logic
circuitry. A typical set of registers are-
i. Data Register(DR):
To hold the data transferred to/ from the processor/ memory. In interfaces
for faster devices there could be a number of data registers
ii. Status Register(SR):
To hold the status information about the I/O device and its interface. The
status information includes-
- readiness of the interface for taking the next command,
- if the device is connected/ powered on, working/ developed fault,
- expecting attention of the processor etc.
The bits in the status registered are assigned to represent these
information.
iii. Command/ Control Register(CR):
To hold the command issued by the processor to the interface.

• Each of the registers in the I/O interfaces is identified by a unique address.

• The decoder logic decodes address specified on the bus to select the
appropriate register for transfer of data, status, or a command.
 The I/O Interface (Contd.)

2. Control logic circuitry:

Logic circuitry to interpret the commands issued by the
processor and to carry these out, to perform the house
keeping operations in the interface and to update the status
register with the status information on the device(s) it serves.

3. Device Interface:
• Device specific Interface with the I/O device
• Possibly as per an I/O bus standard.
Typical I/O Interface
SYSTEM BUS

Data Control Address

Lines Lines Lines

I/O
o o o
Data Register INTERFACE Address I/O INTERFACE
Decoder
Status Register

Command Register
Control
Logic

Device Interface

I/O BUS

I/O Device

Interrupt PwrOn Ready

Bit Bit Bit

Status Register
I/O Address Space
The collection of the addresses of
the registers in the I/O interfaces
constitutes the I/O Address
Space.
The I/O address space is
organized in one of the two ways-
1. Memory Mapped I/O
2. Isolated I/O
I/O Address Space
0 DIC Data Register
1 DIC Address Register
2 DIC Command Register
3 DIC Status Register
4 NIC Data Register
5 NIC Address Register
6 NIC Command Register
7 NIC Status Register
. .
. .
. .
PIC Data Register
PIC Address Register
PIC Command Register
P-1 PIC Status Register
 I/O Address Space
0

Memory mapped I/O:

▪ The addresses of the registers in the
P-1
I/O interfaces are mapped to an area P
in the memory address space itself.
▪ As a result read/write operations on
the I/O interface registers can be
performed as in case of memory
locations.
▪ There is no need for separate control
signal lines in the bus for I/O read/
write operations.
▪ All the processor instructions that are
available for memory operands can N-1
also be used for I/O operands.
 Isolated I/O
▪ In this the I/O address space is totally 0
independent of the memory address
space.
▪ For the read/ write operations on the
I/O interface registers there is a
separate set of control signal lines (I/O
Read & I/O Write) are required to be
provided in the bus.
▪ There is also need for a couple of
additional instructions (Input &
Output) in the instruction set for these
operations. 0

▪ The disadvantage is less flexibility in

programming.
▪ The advantage is that the memory
address space is not fractured and the
P-1 M-1
entire space is available for
instructions and data.
Questions?
Modes of I/O Data Transfer

1. Program Controlled I/O

2. Interrupt Driven I/O
3. Direct Memory Access
 Program Controlled I/O

Printer Data Transfer Routine

Initialize Memory Data Buffer

Pointer and Byte Counter

An Input/Output routine
running on the processor No Printer
carries out the Ready?

Input/Output operations. Yes

Transfer the next byte to
Printer Data Register

Data Transfer
Complete? No
Yes

Return
 Program Controlled I/O
➢ Example I/O Routine:
data_start 1000 ; Data block start address in memory
data_size 500 ; Size of the data block
ready_mask 01 ; Ready bit mask
printer_sr 10 ; Printer interface status register address
printer_dr 11 ; Printer interface data register address
mov #data_start, R0 ; Initialize Memory Buffer Pointer
mov #data_size, R1 ; Initialize Byte Counter
print_loop: tst #ready_mask, @printer_sr ; Busy Wait Loop
bz print_loop
mov (R0)+, @printer_dr ; Transfer data to printer data register
dec R1 " tst " performs
bnz print_loop bitwise AND
operation
return PwrOn Ready
Bit Bit

printer_sr
Disadvantages of Program Controlled I/O

Busy-Wait Loop
➢ I/O devices are normally much slower than the processor.
➢ Busy Wait Loop can be pretty long drawn – for some
devices the loop may have to be executed 100s or even
1000s of times.
➢ The processor remains busy checking the I/O interface
status, not doing anything useful.
➢ Highly inefficient.
Questions?
 Interrupt Driven I/O
▪ Interrupt Driven I/O tries to overcome the “Busy Wait”
problem of Program Controlled I/O.
▪ After a unit of data transfer to the I/O interface the processor,
instead of continuing to check whether the interface has
become ready to receive the next unit of data, it goes onto
carry other pending tasks.
▪ When the interface becomes ready, it calls attention of the
processor by raising an “Interrupt” signal.
▪ On receiving the Interrupt signal the processor puts on hold
the task it is busy with at that moment and goes back to
transfer the next unit of data to the I/O interface.
▪ The wastage of time by the processor in the Busy Wait loop is
avoided.
 Interrupt Mechanism
The basic interrupt mechanism in a computer typically consists of
the following:
• There is an Interrupt Request (IRQ) signal line on the bus that allows
an I/O interface to raise an interrupt request.
• There is an Interrupt Acknowledgement (INTA) signal line using which
the processor indicates acceptance of to the interrupt request.
• The processor interrupts the program currently under execution,
saves the current PC & PS in the stack and transfers control to the
Interrupt Service Routine (ISR) meant for the I/O device concerned.
• After completion of execution of the ISR the processor restores the
saves PC & PS so as to resume execution of the interrupted program.

IRQ
Processor I/O I/O Device
Interface
INTA
 Interrupt Mechanism
Multiple Interfaces with Interrupt Capability:
To allow more than one interface in the computer system to have interrupt
capability there are different possibilities:
1. Provide one IRQ signal line for each interface,
2. Let multiple interfaces share one IRQ signal line.

Processor Processor

IRQ Line
IRQ Lines
I/O Interface I/O Interface I/O Interface I/O Interface I/O Interface I/O Interface

Interrupt identification:
1. Polling
2. Vectored Interrupt
• interrupt vector (PC & PS)
• Interrupt Vector Table (IV Table)
 Multiple Interfaces with Interrupt Capability:
Interrupt identification:
1. Polling
2. Vectored Interrupt
• interrupt vector (PC & PS)
• Interrupt Vector Table (IV Table)

Processor Processor

IRQ Line
IRQ Lines
I/O Interface I/O Interface I/O Interface I/O Interface I/O Interface I/O Interface

Interrupt Vector Table

PC PS
0
1
2

V-1
Simultaneous Interrupts/ Interrupt Priority Mechanisms
• If there are multiple I/O interfaces capable of raising interrupt
request there is possibility that more than one interface raise
interrupt request at the same time.
• The processor has to decide which interface it will service first. While
one interface is serviced the other ones have to wait for their turn.
• There is a question of priority that comes up.
• There is need for an Interrupt Priority mechanism.

IRQ1
INTA1
I/O Interface

Processor
IRQ2
INTA2 I/O Interface

IRQ3
INTA3
I/O Interface
Some of the possible mechanisms
1. Priority Levels:
• In case there are different interrupt request lines each interrupt request
line is assigned a priority level.
• When more than one interface raises interrupt requests simultaneously the
processor compares the priority levels of the corresponding interrupt
request lines.
• Response is sent to the interface using the IRQ with higher priority by
sending INTA to that interface.

IRQ1
INTA1
I/O Interface

Processor
IRQ2
INTA2 I/O Interface
PSR P P P C C C
IRQ3
INTA3 PSR
I/O Interface
 Interrupt Priority Mechanisms
Priority Levels (contd.):
Further,
• The priority level of the currently executing process is specified by the
Priority Bits in the PSR.
• On receiving an IRQ signal the processor compares the priority of the
device with the priority of the current process
• Processor responds to an IRQ only if its priority is higher than that of the
current process.

IRQ1
INTA1
I/O Interface

Processor
IRQ2
INTA2 I/O Interface
P P P C C C
PSR
IRQ3 PSR
INTA3
I/O Interface
 Interrupt Priority Mechanisms

2. Daisy Chaining of Interrupt Acknowledgement (INTA):

IRQ
Processor
INTA
Interface1 Interface2 Interface3

INTA IN INTA OUT

Inhibit

Interface
I R
Status Register
Daisy Chaining of Interrupt Acknowledgement (INTA)
• When more than one interfaces share an IRQ signal line they
also share the same INTA signal line.
• The INTA signal line is daisy chained through the interfaces.
• i.e., the INTA signal line enters one interface, goes through its
logic circuits, comes out to enter the next interface .
• The INTA signal can therefore propagate through the interfaces.
• An interface does not allow the signal to propagate through it if
it is one of the interfaces raising interrupt request.
• The first interface in the chain among the interfaces raising IRQ
receives the INTA signal and gets the chance to place its
identification code on the data bus to obtain service from the
processor while the rest have to wait for their turn.
• Hence the sequence of the interfaces in the daisy chain defines
the interrupt priority among the interfaces sharing the IRQ, INTA
pair. The interface nearest to the processor has the highest
priority.
 General Interrupts Structure
Processor
IRQ1

INTA1
Interface1 Interface2 Interface3

IRQ2

INTA2
Interface1 Interface2 Interface3

IRQk

INTAk
Interface1 Interface2 Interface3
 Steps involved in the process of interrupts
(with Vectored Interrupt)
1. The I/O interface raises the IRQ
2. The processor starts interrupt processing by comparing the priority level of
the IRQ with the priority level of the current process (i.e. the priority level
in PSR). If the priority level of the IRQ is found to be higher then it
interrupts the current process, saves its PC and PS in the stack and issues
the appropriate INTA.
3. Else the interrupt processing is deferred until the priority level in PSR is
modified.
4. In response to the INTA the interrupting interface places its identification
code on the data bus and removed the IRQ.
5. The processor reads identification code from the bus, extracts the
interrupt vector from the IV-table, modifies PC and PSR accordingly to
transfer control to the IRS of the I/O device.
6. The ISR is executed to provide the required service to the device.
7. On completion of execution of the ISR the saved PC, PS values are restored
so that execution of the interrupted process is resumed.
Questions ?
Provision for Interrupts in the Instruction Execution Loop

• It is necessary to provide for recognition of the event of raising of an

interrupt request in the instruction execution loop.
• Normally, it is done by the control unit of the processor checking the
IRQ lines after the completion of execution of an instruction or
before starting of fetching of a new instruction.
• The instruction execution loop is modified as follows:
Repeat
If any Interrupt Request Activated Process Interrupt
MAR  PC
PC++
Read
IR  MDR
Execute
Until IR = Halt
Process Interrupt Micro-routine
Process Interrupt
{Check if the priority of the IRQ is lower than priority of executing process
then return
else {
Issue INTA
Identify Interrupting Device
Save current PC, PS
Load Interrupt Vector to PC, PS
}
}
• At the beginning of the loop the control unit checks the IRQ lines.
• If it finds any of the IRQs activated it jumps to a routine that processes the
interrupt.
• After the interrupt response is initiated the control returns to the repeat loop
for normal instruction execution.
• Interrupts are not recognized during the execution of an instruction.
Questions ?
Triggering and Enabling/Disabling of Interrupts
• Level Triggering
• The voltage level at the IRQ signal line
Q Set
indicates raising of an interrupt. The
processor looks at the voltage level of the FF
IRQ line. Clr
• Edge Triggering
• The processor recognizes the raising of an
interrupt on detection of a transition Q Set
(low to high or high to low) in the voltage FF
level in the IRQ. The voltage level itself is Clr
not important in this case
• Interrupt Masking
• Provision for disabling one or more of the FF IRQ1
IRQ signal lines. IRQ2
FF
• Enabling and disabling of interrupts IRQ3
FF
• Provision for enabling/ disabling all the IRQ4
FF
IRQ signal lines.
Mask 1 0 1 0
Questions ?
Exceptions, Traps, Software Interrupts
and Privilege Levels

Some Special Situations/ Mechanisms that are

handled in similar fashion as the Interrupts
 Exceptions
• Exceptions refer to events occurring internal to the processor that
cause a interruption to the execution of the current program.
Examples of exceptions-
▪ Occurrence of an illegal instruction.
▪ An illegal instruction exception occurs when the processor
encounters an illegal instruction.
▪ Occurrence of a Bus Error/ Page Fault.
▪ A bus error occurs when a bus cycle is initiated at an address that is
physically not available.
▪ A page fault is a condition that occurs in virtual memory when an
operation is initiated on a memory location in a page that has not
been loaded to the physically memory.
▪ Occurrence of divide by zero condition
▪ A divide by zero condition occurs when in a divide operation the
divisor turns out to be a zero as there is no binary representation for
infinity. The ALU cannot handle it.
 Exceptions
➢ When an exception occurs a routine provided for handling the
specific condition gets executed.
▪ For Illegal Instruction exception, a routine that perhaps prints a
message like “Illegal Instruction Encountered” and then
terminates the current program is executed.
▪ In case of Bus Error the routine may print a message like “Bus
Error” and then terminate the program.
▪ For Page Fault the routine will locate the page in the virtual
memory and load it to the physical memory so that the memory
access can be completed.
▪ For Divide by Zero the routine has to take an appropriate action,
such as, printing “Divide by Zero” or providing a signal to the
processor indicating that the result is “Infinity”.
 Traps

▪ Traps are special mechanisms to trap the program

during execution to make it pause.
▪ Traps such as- Breakpoint, Trace etc. are used for
debugging or for program instrumentation and
performance analysis purposes.
▪ Special instructions are provided in the instruction
set of the processor for traps.
 Traps
Traps for Debugging:
▪ Normally when a program gets control of the processor it
continues execution until completion or a fault condition occurs.
▪ For debugging a program it is necessary to know the status of
the variables of the program at different points in its execution.
▪ To do that the program has to be halted at desired points and
control is transferred to the variable/ status access routine.
▪ The access routine allows the programmer to read/ modify the
variables/ status.
▪ Once the job is done the control is transferred back to the
program.
▪ Special trap instructions are provided in the instruction set of a
processor. Trap instructions are inserted at appropriate points in
the program. The Trap Service Routine transfers control to the
debugger program.
 Traps

Traps for program instrumentation:

▪ Program instrumentation involves collecting program
execution statistics such as- Execution times of program
segments/ execution paths, Bottle-necks.
▪ These are to help in programs Performance Optimization,
Reliability Enhancement, Vulnerability Elimination etc. by
identifying the Bottle Necks, Race Conditions, Vulnerabilities
in the programs.
 Software Interrupts
• A software interrupt is caused by execution of an instruction
provided for the purpose. Execution of the software interrupt
instruction causes execution of an ISR.
• After completion of execution of the ISR control returns to the
interrupted program.
• Therefore, it is in a way like execution of a subroutine. Its
difference w.r.t. a subroutine call lies in the following:

1. The program causing the software interrupt does not provide

the address of the routine. This is obtained from the Interrupt
Vector.
2. Before transferring control to the ISR the Processor Status
Register (PSR) content is changed with that provided in the
interrupt vector.
 Software Interrupts

Software interrupts are used by application programs for obtaining

operating system services.
• The OS services are encoded in routines within the OS.
• The memory addresses of these routines are not known to the
applications. Therefore, these routines cannot be executed by the
application programs through subroutine calls.
• These addresses are made available to software interrupts through
the interrupt vector.
Processor Execution Mode – Privilege Level
There is another important aspect associated with
execution of OS service routines.
• The OS service routines can be executed only with a higher
privilege level than that of an application-level program.
• That is because, an application-level program should not be
allowed direct access to the system resources. This
restriction is required to protect these resources from
unauthorized malicious access as well as faulty access by
untested and defective code.
• Therefore, only tested OS service routines are allowed
access to the sensitive resources in the system and that is
done through privilege levels.
Processor Execution Mode – Privilege Level
• The privilege level of a process is encoded in a few bits in the
processor status register known as Privilege Bits or Processor Mode
Bits.
• When a new PS value given in the interrupt vector is loaded to the
PSR before transferring control to the ISR of the software interrupt,
the process assume the privilege level required for execution of the
OS service routine.
• This change in privilege level of the process from application or user
level to that of OS or Supervisory level is called a Context Switch
- a switch of context from application or user context to an OS or
supervisory context.
• This Context Switch occurs is case of all interrupts (Hardware and
Software) as well as for exceptions. At the completion of execution
of the ISR a reverse switch from supervisory context to user context
occurs.
Privilege Level Bits in Processor Status Register

Processor
Pr Pr P P P C C C C C

Processor Status Register (PSR)

PSR
Hardware Interrupts Vs Software Interrupts
A software interrupt differs from a (hardware)
interrupt in the following-
• Identification of the interrupt is automatic from the
interrupt instruction. Hence the appropriate interrupt
vector can be readily extracted from the Interrupt Vector
Table.
• In software interrupt the task performed by the ISR is
initiated by the process under execution and is very much a
part of that process.
• In case of hardware interrupt the task performed by the IRS
executed due to the interrupt may be caused by an event
not due to the interrupted process under execution and
may in no way be related to it.
Questions ?
 Direct Memory Access (DMA)

• In Program Controlled and Interrupt Driven I/O, the processor

executes routines to carry out each byte of data transfer. The
processor initiates as well as performs the transfer of the
individual bytes to/from the I/O Interface.
• In DMA the processor is freed from transferring the individual
bytes of data. The processor only initiates the process of data
transfer.
• I/O interface is empowered to perform the actual transfer of
the individual bytes of the data to/from the memory unit.
• The Processor initiates the transfers in a blocks at a time.
 Direct Memory Access (DMA)
• The processor initiates the I/O operation by invoking an ISR.
• The ISR supplies the start address of the data block in memory and the
size of the data block to be transferred to the I/O interface and
specifies the operation to be performed.
• The I/O interface then carries out the actual transfer of the data units
in the data block one by one on its own by directly accessing the
memory unit without involving the processor.
• While this I/O data transfer operation is carried out by the I/O
interface the processor makes itself busy in the execution of some
other process.
• After the entire data block transfer is complete the interface raises the
interrupt request (IRQ) signal to inform this status to the processor.
• The processor, on receipt of the IRQ, interrupts the process it is busy
with and invokes the ISR to issue the next command to the interface.
• After giving the command to the interface the processor resumes
execution of the interrupted process.
 Direct Memory Access (DMA)
The DMA mechanism brings efficiency in the
following ways-
1. It reduces the number of bus cycles required for the transfer
of a block of data between memory and an I/O device to half
- in DMA the data need not go through a processor register.
1. Reduces the overhead of instruction execution in the ISR per
unit of data transfer – the ISR needs to be executed only
once for a large block of data instead of every byte/word of
data transfer.
2. Leads to better utilization of the resources in the computer
system – Frees the processor from I/O data transfer activity
and allows it to devote its time in useful process activities and
makes higher degree of multiprogramming possible.
 PROCESSOR MEMORY
Program Controlled/ DMA
Interrupt Driven I/O

SYSTEM BUS

I/O I/O
I/O INTERFACE o o o I/O INTERFACE
INTERFACE INTERFACE
without DMA with DMA

I/O
I/O DEV
I/O
DEV DEV I/O I/O
DEV DEV
I/O I/O
DEV DEV
I/O BUS I/O I/O
DEV DEV
I/O I/O I/O
DEV DEV DEV
 Requirements for DMA
• For DMA the I/O interface needs to access the memory unit by
itself.
• Requires the capability of driving the bus.
• Be able to become a bus master,
• Be able to generate a memory address and place it on the bus,
• Be able to issue read/ write command to the memory unit.
• A DMA interface typically has the following:
• a start address register,
• a word/ byte count register,
• an address counter, and
• the normal set of I/O interface registers, namely,
• data register,
• command register,
• status register
 CPU Memory
SYSTEM BUS

Data Address Control

Lines Lines Lines
Start Address Address
Register Counter o o o

Data Register Address Decoder

I/O
Word/ Byte Control
Interface
Counter Logic

Status Register

Command Register I/O

Interface

Device Interface (as per I/O Bus Requirements)

I/O BUS

Typical I/O Interface with DMA Capability

 Typical DMA Process

• To initiate a DMA operation the ISR for the interface performs

the following:
o Transfer the start address of the memory block for data transfer
and the size of the data to be transferred to the start address
register and the word count register respectively.
o Write the command in the command register of the interface.
• After that the ISR transfers control of the processor back to the
interrupted program.
• On receiving the command the interface performs the data
transfer as follows:
Contd..
 Typical DMA Process (contd..)
On receiving the command, the interface performs the data transfer as
follows:
1. Clear the ready bit in the status register in the interface.
2. Transfer the start address to the address counter.
3. Get mastership of the bus, enable the address counter content on to the
address bus and initiate read or write operation on the memory location as
per the command.
4. Perform a data transfer operation from memory to the interface data register,
if the command specifies a data transfer operation from memory to device.
Else, perform a data transfer operation from the interface data register to
memory, if the command specifies a data transfer operation from device to
memory.
5. On completion of the memory operation release the bus mastership,
increment the address counter, decrement the word counter.
6. Repeat steps 3 to 6 until the word count becomes zero.
7. Set the ready bit and writes the successful completion code in the interface
status register.
8. Raise an interrupt request.
 Modes of DMA
A DMA interface performs data transfer operations in one of the two
following modes-
1. Cycle Stealing Mode:
• In this mode normally the processor is assumed to be the bus master.
• When the bus is not in use by the processor, the DMA interface gets
hold of the bus, performs one bus cycle for memory operation and
then releases the bus.
• This mode is normally used in interfaces for slower devices.

2. Burst/ Block Mode:

• In this mode the interface obtains bus mastership, performs a burst
of data transfers to/from memory and then releases the bus.
• This is normally used in high speed devices.
• To operate in this mode the interface maintains a data buffer capable
of holding several bytes/ words of data instead of a single data
register.
Questions ?
Thank You