Computer Architecture & Microcontrollers_ MODULE 5_S4 EC KTU

Module 5: Part 2

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Input/Output Organization – Introduction, Synchronous vs. asynchronous I/O, Programmed I/O, Interrupt
driven I/O, Direct Memory Access.

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Input/Output Organization

Introduction to Input/Output Organization

• Three most essential building blocks of any computer are

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1) processor,
2) memory system and
3) input/output modules.
•

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Any type of computer must offer some peripheral devices for interacting with other devices and
communicating with external world.

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• The I/O module contains logic for performing a communication function between the peripheral
and the bus.
• All peripheral devices, which are externally interfaced with computer (sometimes called as host)
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through its chassis, have their own processors within the devices.
• Therefore, communication between a host and any one of its peripheral units is essentially the
communication between two processors.
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Computer Printer
I/O
Communication
Processor I/P Port I/P Port Processor
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Interface
Host Motherboard Peripheral PCB
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General structure of any link between a host and its peripheral unit

• This communication link is always established through the external world with the help of wire
connections.
• Certain special points may be observed in Figure.

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• First, the processors in motherboard of the host (computer) and all other processors within

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peripherals are generally different and have their own operating frequencies.
• Second, these processors are never directly interconnected and but through some I/O ports.
All necessary signals and data between any two processors are transferred through these ports.

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• Third, and most important point is, the method of data communication between host and its
peripheral may be any one of the following three
1) Programmed I/O
2) Interrupt driven I/O

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3) Direct Memory Access (DMA)

I/O Mapped I/O vs Memory Mapped I/O

(Methods of Interfacing I/O)

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Let's take an example of the 8085 processor. It has 16 address lines i.e. addressing capacity of 64 KB

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memory. It supports I/O-mapped I/Os. It can address up to 256 I/Os.

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Memory Mapped I/O

(Bus Master)
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(System Bus)
Read
Write
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Processor

Memory
I/O Devices
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Devices

(Bus Master) I/O Mapped I/O

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(System Bus)
Memory Read
Memory Write
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I/O Read
Processor I/O Write

Memory
I/O Devices
Devices
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I/O Mapped I/O Memory Mapped I/O

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I/O devices are mapped into I/O space I/O devices are mapped into memory space
I/O devices are allotted I/O addresses. I/O devices are allotted memory addresses.
Processor differentiates between I/O devices Processor does not differentiate between memory

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and memory. It isolates I/O devices.
I/O addresses are smaller than memory
addresses. E.g.: in 8085, I/O addresses will be 8
bits though memory addresses are 16-bit
and I/O. Treats I/O devices also like memory devices.
I/O addresses are as big as memory addresses. E.g.:
in 8085, I/O addresses will be 16 bits as memory
addresses are also 16-bit

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This allows us to access limited number of I/O This allows us to increase the number of I/O devices.
devices. E.g: in 8085, we can access up to 2 16 = 65536 I/O
E.g: in 8085, we can access only up to 28 = 256 devices.
I/O devices.

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We can transfer data from I/O device using We can transfer data from I/O devices using any

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dedicated I/O instructions like IN and OUT only
Data can be transferred only using a fixed
register. E.g.: in 8085 only “Accumulator”
register
We need four control signals: Memory Read,
Memory Write and I/O Read and I/O Write
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I/O addresses are smaller so address decoding
instruction like MOV etc.
Data can be transferred using any register of the
processor.
We need only two control signals in the system:
Read and Write.
Memory addresses are big so address decoding will

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will be faster. be slower
Address decoding will be simpler and cheaper. Address decoding will be more complex and costly
Eg: 8085, 8086 microprocessor (default setting) Eg: 8051 microcontroller
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Both memory mapped I/O as well as I/O

mapped I/O schemes are supported by 8085.

Synchronous vs. asynchronous I/O

• Data transfers can be synchronous or asynchronous.
Synchronous Transmission Asynchronous Transmission
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In Synchronous transmission, a common clock Asynchronous transmission has no need of

governs the communication between any two synchronized clocks.
devices. Therefore, help of some additional handshaking
signals are sought out to complete the transmission.
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(eg: Start bit and Stop bits)

Data is sent in form of blocks or frames. Data is sent in form of byte or character.
complete the data transaction as per Due to the absence of any common clock-source
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predefined schedule. between these two, there cannot be any predefined

time duration for completion of data transfer
time interval of transmission is constant time interval of transmission is random.
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Fast and Costly Slow and economical

There is no gap present between data. There is gap present between data.
Efficient use of transmission line is done in While in asynchronous transmission, transmission line
synchronous transmission. remains empty during gap in character transmission.
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In this scheme, CPU execution waits while I/O proceeds concurrently with CPU execution
I/O proceeds
• Which is more efficient with respect to processor utilisation? Justify your answer
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Synchronous I/O − In this scheme CPU execution waits while I/O proceeds
hence system time wasted
Asynchronous I/O − I/O proceeds concurrently with CPU execution
hence system time is not wasted
Asynchronous I/O is more efficient with respect to processor utilisation

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Programmed I/O (or Polling)

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• Processor periodically checks (polls) the status of every I/O device to know if it wants to perform a
data Transfer.
•

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For programmed I/O, a complete attention of the processor is essential for the data communication,
• Programmed I/O is also designated as polling method of data transfer or simply by the term polling.
• Processor is busy in constantly checking all I/O devices, hence system time wasted.
• Additional hardware not required
• System is cheaper and less complex.

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Interrupt Driven I/O
• In interrupt driven I/O, the transfer is not initiated by the processor.

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• Instead, an I/O device which wants to perform a data transfer with the processor, must give an
interrupt to the processor.

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• An interrupt is a condition that makes the processor execute an ISR (Interrupt Service Routine).
• In the ISR, processor will perform data Transfer with the I/O device.
• This relieves the processor from periodically checking the status of every I/O device thereby saves
as lot of time of the processor.
• The processor is free to carry on its own operations.
• Whenever a device wants to transfer data, it will interrupt the processor.
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• This is how many I/O devices Transfer data with the processor.

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• E.g.: Keyboard. Instead of the processor checking all the time, whether a key is pressed, the
keyboard interrupts the processor as an when we press a key. In the ISR of the keyboard, which is a
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part of the keyboard driver software, the processor will read the data from the keyboard.
• Hence interrupt driven I/O is much better than Polled I/O (Programmed I/O).
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Note: Interrupt Driven I/O Vs Polling (Programmed I/O)

Interrupt Driven I/O Polling (Programmed I/O)

I/O device interrupts the processor whenever it Processor periodically checks (polls) the status of
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wants to perform a data Transfer. every I/O device to know if it wants to perform a
data Transfer.
Processor is free to carry on its own operations, Processor is busy in constantly checking all
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hence saves system time. I/O devices, hence system time wasted.
Additional hardware required to handle interrupts. Additional hardware not required
E.g.: 8259 Programmable interrupt controller.
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Increases cost and complexity of the system. System is cheaper and less complex.
Interrupt priority has to be managed through No such issue.
software or through hardware.
Interrupt vector addresses (ISR Addresses) need to No such issue.
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be stored in an Interrupt Vector table - IVT.

Which is more efficient with respect to processor utilisation? Justify your answer
• In case of Programmed I/O, Processor is busy in constantly checking all I/O devices, hence system
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time wasted.
• In case of Interrupt Driven I/O, Processor is free to carry on its own operations, hence saves
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system time.
• E.g.: Keyboard. Instead of the processor checking all the time, whether a key is pressed, the
keyboard interrupts the processor as an when we press a key. In the ISR of the keyboard, which is a
part of the keyboard driver software, the processor will read the data from the keyboard.
• Hence interrupt driven I/O is much better than Polled I/O (Programmed I/O).

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Direct Memory Access (or DMA based I/O)

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• DMA means transferring data directly between memory and I/O.
• DMA transfers are very fast as compared to Processor based transfers due to two reasons.

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1) They are hardware based so no time is wasted in fetching and decoding instructions.
2) Transfers are directly between memory and I/O without data going via the Processor.
• To Perform a DMA transfer we need a DMA Controller like 8237/ 8257.
• It is capable of taking control of the system bus from the Processor.

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System Bus Memory

Processor

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HLDA HRQ

DREQ
DMA Peripheral device
Controller DACK (disk controller)
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DACK = DMA acknowledge
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DREQ = DMA request

HLDA = HOLD acknowledge
HRQ = HOLD request
System Bus = Address bus + Data bus + Control bus
The process is performed as follows.
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1) By Default, Processor is the bus master.

2) The DMA transfer parameters are first initialized by the processor.
3) Processor programs two registers inside the DMAC called CAR and CWCR giving the starting address
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and the number of bytes to be transferred.

4) DMAC now ensures that the I/O device is ready for the transfer by checking the DREQ signal.
5) If DREQ=1, then DMAC gives HOLD signal to the Processor requesting control of the system bus.
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6) Processor releases control of the bus after finishing the current machine (bus) cycle.
7) Processor gives HLDA informing DMAC that it is now the bus master.
8) DMAC issues DACK# (by default active low, but can be changed) to I/O device indicating that the
transfer is about to begin.
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9) Now DMAC transfers one byte in one cycle.

10) After every byte is transferred, the Address register and Count register are decremented by 1.
11) This repeats till Count reaches “0” also called Terminal Count.
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12) Now the transfer is complete.

13) DMAC returns the system bus to Processor by making HOLD = 0.
14) Processor once again becomes bus master.
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• Advantage of DMA: DMA transfers are very fast.

• Drawback of DMA: DMAC becomes the bus master. Hence during DMA cycles, the processor cannot
perform any operations as the bus is already being used for DMA. The processor remains in HOLD
state.
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Note : Types / Methods / Techniques Of DMA Transfers

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8237 has four modes of data transfer:

1) Block Transfer Mode / Burst Mode

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• In this mode, the DMAC is programmed to transfer ALL THE BYTES in one complete DMA
operation.
• After a byte is transferred, the CAR and CWCR are adjusted accordingly.
• The system bus is returned to the processor, ONLY after all the bytes are transferred.

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• It is the fastest form of DMA but keeps the processor inactive for a long time.
2) Single Byte Transfer Mode/ Cycle Stealing
• Once the DMAC becomes the bus master, it will transfer only ONE BYTE and return the bus to

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the processor. As soon as the processor performs one bus cycle, DMAC will once again take the
bus back from the processor.

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• Hence both DMAC and processor are constantly stealing bus cycles from each other.
• It is the most popular method of DMA, because it keeps the processor active in the background.
• After a byte is transferred, the CAR and CWCR are adjusted accordingly.
3) Demand Transfer Mode
• It is very similar to Block Transfer, except that the DREQ must remain active throughout the
DMA operation.
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• If during the operation DREQ goes low, the DMA operation is stopped and the busses are

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returned to the processor. #Please refer Bharat Sir's Lecture Notes for this ...
• In the meantime, the processor can continue with its own operations. Once DREQ goes high
again, the DMA operation continues from where it had stopped.
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• This means, the transfer happens on demand from the I/O device, hence the name.
4) Hidden Mode / Transparent Mode
• In this mode, once the processor programs all parameters inside the DMAC, the DMAC does
not request the processor for the control of the bus.
• Instead, it observes the processor. It waits for the processor to enter idle state.
• Once the processor is idle, the DMAC will take control of the bus and perform the Transfer.
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• So, the Transfer is totally transparent to the processor or hidden from the processor.
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Note: The technique of data transmission in programmed I/O and interrupt driven I/O is generally
asynchronous, and during DMA it is synchronous.
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