8086-Special Purpose Programmable

Devices and their Interfacing

Deepak
D k JJohn
h
SJCET-Palai
 Data transfer schemes
 To transfer information between CPU and physical I/O devices,
may use the following techniques:

Data transfer schemes

Memory mapped
Programmed I/ O
pp
I/O mapped

Interrupt driven I/ O

Direct memory access

 P
Programmed
d I/O
 Data
ata ttransfer
a s e iss acco
accomplished
p s ed tthrough
oug aan I/O
/O po
portt co
controlled
t o ed
by software
 I/O operations
p are completely
p y controlled byy pprocessor, then the
system is said to be using “ Programmed I/O”
 Processor has to check I/O system periodically until the operation
completes  “POLLING”
 Microprocessor has to check if any device need service.
 When Programmed I/O techniques is used:
I. Processor fetches I/O related instructions from memory and
Issues I/O commands to I/O system to execute the instruction.
II. Memory Mapped I/O & I/O mapped I/O technique may apply.
III. Processor has 2 separate instructions IN & OUT for data
t
transfer.
f
IV. When the I/O instruction is encountered by the processor the
I/O port is expected to be ready to response.
response
 Memory-mapped I/O
 Reading and writing are similar to memory read/write
 Uses same memory read and write signals
Memory Address Space
 Most processors use this I/O mapping

I/O Address Space

(a)
( ) Separate
S t I/O and
d memory space (b) Memory-mapped
M d I/O (c)
( ) Hybrid
H b id
 I/O mapped
Separate I/O address space
Separate I/O read and write signals are needed
Uses IN and OUT instructions

Memory Address
Space I/O address Space

Total Address Space

 M
Memory M d I/O
Mapped M d I/O
I/O Mapped
Memory & I/O share the entire Processor provides separate
address range of processor address range for memory & I/O
Processor provides more address Less address lines for accessing
li
lines f accessing
for i memory I/O
More Decoding is required Less decoding is required
Memory control signals used to I/O control signals are used to
control Read & Write I/O control Read & Write I/O
operations operations
 I t
Interrupt
t I/O
 Overcomes CPU waiting.
 No repeated CPU checking of device, No need to poll device status.
 I/O device interrupts the processor and initiate data transfer
 I/O module interrupts when ready
 As soon as the
A h CPU finishes
fi i h theh current instruction,
i i i transfers
it f
its execution to an interrupt-service routine which responds to the
external
t l interrupt.
i t t
Basic Operation
I. CPU issues read command.
II. I/O module ggets data from pperipheral
p while CPU does other
work.
III. I/O module interrupts CPU.
IV. CPU requests data.
V. I/O module transfers data
 Direct Memory Access
 It is a technique of transferring data between memory and I/O devices
without
ih CPU intervention.
i i
 CPU sets up transfer with DMA controller; then transaction occurs
without
ith t CPU .
 DMA channel: system pathway used by a device to transfer
information directly to and from memory.
memory
 DMA controller: dedicated hardware used for controlling the DMA
operation.
operation
 x86 Interrupt Pins
 HOLD: DMA request.
request
 HLDA: DMA acknowledge signal.
3 techniques:
1. Block
l k transfer
f
- whole data block transferred
- CPU can do non-related bus activities in the meanwhile
2. Cycle stealing
- DMA controller freezes the CPU, and then does a DMA while
CPU frozen
- word-by-word transfer
3. Interleaved
- DMA controller uses CPU cycles that aren't using the bus,
 DMA Controller 8257
Features:
 It is a 4-channel DMA.
 So 4 I/O devices can be interfaced to DMA.
 It is designed by Intel.
 Each channel have 16-bit address and 14 bit counter.
 It provides chip priority resolver that resolves priority of channels
in fixed or rotating mode.
Functional Block diagram
It containing Five main Blocks.
Blocks
1. DMA channels
2. D t bus
Data b buffer
b ff
3. Read/Write logic
4. C
Controll logic
l i block
bl k
5. Priority resolver
DMA channels
 Each of four channels of 8257 has a pair of two 16-bit registers,
named DMA address register (store the address of the starting
memory location, which will be accessed by the DMA Channel) and
terminal count register(used for ascertaining that the data transfer
through a DMA channel ceases or stops after the required number of
DMA cycles.).
 There are two common registers
g for all the channels,, namely,
y, mode set
register and status register.
 Thus there are a total of ten registers. The CPU selects one of these
ten registers using address lines Ao-A3.
 The count register is used to count the number of byte or word
f d by
transferred b DMA. The
h format
f off count register
i i
is,

 14-bits B0-B13 is used to count value and a 2-bits is used for indicate
the type of DMA transfer (Read/Write/Veri1 transfer).
Data Bus Buffer:
 It contain 8 bit bi-directional buffer.
 Slave mode ,it transfer data between microprocessor and internal
data bus.
 Master mode ,the outputs A8-A15 bits of memory address on data
li
lines (U idi i l)
(Unidirectional).
Read/Control Logic:
 It control all internal Read/Write operation.
 Slave mode ,it accepts address bits and control signal from
microprocessor.
i
 Master mode ,it generate address bits and control signal.
Control logic block:
 It contains
i ,
1. Control logic
2. Mode set register
3. Status Register.
Control Logic:
 Master mode ,It control the sequence of DMA operation during all
DMA cycles.
 It generates address and control signals.
 It activate a HRQ(Hold ReQuest) signal on DMA channel Request.
 Slave mode, it is disabled.
Mode Set Registers:
It is a write only registers.
registers
It is used to set the operating modes.
This registers is programmed after initialization of DMA channel.
The use of mode set register is,
is
1. Enable/disable a channel.
2. Fixed/rotatingg p
priorityy
3. Stop DMA on terminal count.
4. Extended/normal write time.
5. Auto reloading of channel-2.
Status Registers:
 It is read only registers, It tell the status of DMA channels.
 These status bits are cleared after a read operation by microprocessor.
microprocessor
 Update flag is not affected during read operation and a one in this bit
position indicates that the channel-2 register has been reloaded from
channel-3 registers in the auto load mode of operation.
 The UP bit is set during update cycle . It is cleared after completion of
update cycle.
Interfacing 8257 with 8086
 Thee DMA co controller
t o e sesends
ds a HOLD
O request
equest to tthee C
CPU
U aandd wa
waits
ts for
o
the CPU to assert the HLDA signal. The CPU relinquishes the
control of the bus before asserting the HLDA signal.
Programmable Interval Timer 8253 (PIT)
Features
1. Three 16-bit independent counters.
2. Three counters are identical pre-settable, and can be programmed
f either
for ith binary
bi or BCD count.t
3. Counter can be programmed in six different modes.
4 Compatible with all Intel and most other microprocessors.
4. microprocessors
5. can operate upto 2.6 MHz.
6. Used for controlling real time events RT clock, events counter etc
Block Diagram
Counter
 Each counter is assigned an individual port address.
 The control register common to all 3 counters.
 Each counter in the block diagram has 3 lines connected to it.
 Two of these lines,, clock and g
gate,, are inputs.
p The third,, labeled OUT
is an output.
 The function of these lines changes and depends on how the device is
initialized or programmed.
control word
 Allows the programmer to select the counter, model of operation,
bi
binary or BCD count andd type off operation
i
Data Bus Buffer
 bi-directional, 8-bit buffer is used to interface the 8253 to the system
data bus.
 The Data bus buffer has three basic functions.
1. Programming the modes of 8253/54.
2. Loading the count registers.
3. Reading the count values.
Operation Modes
Mode 0: Set Output Bit when timer done.
 The output will start off zero. The count is loaded and the timer
will
ill start
t t to
t countt down.
d
 When the count has reached zero the output will be set high, and
remain high until the next count has been reloaded.
reloaded
Mode 1: Programmable One-Shot.
 The output will go low following the rising edge of the gate input.
 The
Th counter will
ill count andd the
h output will
ill go high
hi h once the
h counter
has reached zero.
.
Mode 2: Rate Generator.
 The counter will continually count down,
down when the count reaches
zero, the output will pulse low and the counter will be reloaded
Mode 3: Square Wave Generator.
 This mode is similar to Mode 2 except the output t t remains low for
half of the timer period and high for the other half of the period.
Mode 4: Software Triggered Pulse.
 The output
p will remain high g until the timer has counted to zero,, at
which point the output will pulse low and then go high again.
Mode 5: Hardware Triggered Pulse.
 The counter will start countingg once the ggate input
p g goes high,
g when
the counter reaches zero the output will pulse low and then go high
again.
 P
Programmable
bl Interrupt
I t t Controller
C t ll 8259
The Programmable Interrupt Controller (PIC) functions as an overall
manager in an Interrupt-Driven system environment.
 Able to handle a number of interrupts at a time.
 Takes care of a number of simultaneously appearing interrupt requests
along with their types and priorities.
 Compatible with 8-bit
8 bit as well as 16-bit
16 bit processors.
processors
 deal with up to 64 interrupt inputs.
 interrupts
te upts ca
can be masked.
as ed.
 various priority schemes can also programmed.
8259A PIC- BLOCK DIAGRAM
It includes 8 blocks.
 Control logic
 Read/Write logic
 Data bus buffer
 Three registers (IRR,ISR and IMR)
 Priority resolver
 Cascade Buffer
Interrupt Request Register (IRR) and In-Service Register (ISR)
 The
h interrupts
i at the
h IR input
i li
lines are handled
h dl d by b two registers
i i
in
cascade, the Interrupt Request Register (lRR) and the In- Service
Register (lSR).
(lSR)
 The IRR is used to indicate all the interrupt levels which are
requesting service.
service
 ISR is used to store all the interrupt levels which are currently being
serviced
Priority Resolver
 This logic block determines the priorities of the bits set in the lRR.
 The highest priority is selected and strobed into the corresponding bit
of the lSR duringg the INTA sequence.
q
Interrupt Mask Register (IMR)
 The lMR stores the bits which disable the interrupt lines to be masked.
 The IMR operates on the output of the IRR.
Data Bus Buffer
 This bidirectional 8-bit buffer is used to interface the 8259A to the
system Data Bus.
 Control words and status information are transferred through the Data
Bus Buffer
Read-Write Logic
 accept OUTput commands from the CPU. CPU
 contains the Initialization Command Word (ICW) registers and
Operation Command Word (OCW) registers which store the various
control formats for device operation.
 allows the status of the 8259A to be transferred onto the Data Bus
The Cascade Buffer/Comparator
 stores and compares the IDs of all 8259A's used in the system. The
associated three I/O pins (CAS0-2) are outputs when the 8259A is
used as a master and are inputs when the 8259A is used as a slave.
 As
A a master, the
h 8259A sends d the
h ID off the
h interrupting
i i slave
l d i
device
onto the CAS 0-2 lines. The slave thus selected will send its
preprogrammed subroutine address onto the Data Bus during the
next one or two consecutive INTA pulses.
Interfacing 8259 with 8086
IInterrupt
t t Sequence
S
1. One or more of the INTERRUPT REQUEST lines are raised high,
setting the corresponding IRR bit(s).
bit(s)
2. The 8259A evaluates these requests, and sends an INT to the CPU, if
appropriate.
i t
3. The CPU acknowledges the INT and responds with an INTA pulse.
4 Upon
4. U receiving
i i an INTA from f the
h CPU , the
h highest
hi h priority
i i ISR bit
bi is
i
set and the corresponding IRR bit is reset.
5 The 8086 will
5. ill initiate another two
t o INTA pulses.
p lses
6. This completes the interrupt cycle. In the AEOI(Automatic End of
Interrupt) mode the ISR bit is reset at the end of the second INTA
pulse. Otherwise, the ISR bit remains set until an appropriate EOI(End
of Interruptp Mode)) command is issued at the end of the interrupt p
subroutine.
PROGRAMMING THE 8259A
 The 8259A accepts two types of command words generated by the
CPU:
1 Initialization
1. I iti li ti Command
C d Words
W d (ICWs):Before
(ICW ) B f start
t t functioning,
f ti i 8259
must be initialized by writing two to four command words into their
respective command word registers.
registers
2. Operation Command Words (OCWs): These are the command words
which command the 8259Ato operate in various interrupt modes.
8259A- OPERATING MODES
1 FULLY NESTED
1.
2. AUTOMATIC ROTATION
3 SPECIFIC ROTATION
3.
4. END OF INTERRUPT
5 AUTOMATIC EOI
5.
1. FULLY NESTED
 General
G l purpose mode,
d All IRs
IR are arrangedd from
f hi h t to
highest t lowest.
l t
 IR0 Highest IR7Lowest
2 AUTOMATIC ROTATION MODE
2.
 In this mode, a device after being serviced, receives the lowest
priority.
priority
3. SPECIFIC ROTATION MODE
 Similar to automatic rotation mode, except that the user can select
any IR for the lowest priority, thus fixing all other priorities.
4. END OF INTERRUPT (EOI)
 After the completion of an interrupt service, the corresponding ISR
bi needs
bits d to beb reset to update
d the
h information
i f i ini the
h ISR.
ISR This
Thi is
i
called EOI command
5 AUTOMATIC EOI
5.
 In this mode, no command is necessary.
 During
D i the th third
thi d interrupt
i t t acknowledge
k l d cycle,l the
th ISR bit is
i reset.
t
8251A pprogrammable
g Communication Interface
 USART (Universal Synchronous Asynchronous Receiver
Transmitter)
i )
 designed for synchronous /asynchronous serial data
communication,
i ti packaged
k d in i a 28-pin
28 i DIP.
DIP
 Receives parallel data from the CPU & transmits serial data after
conversion.
conversion
 Also receives serial data from the outside & transmits parallel data
to the CPU after conversion.
conversion
Block diagram
F ti l Blocks
Functional Bl k off 8251A
1. Data Bus buffer
2 Read/Write Control Logic
2.
3. Modem Control
4 Transmitter
4.
5. Receiver

1. Data Bus Buffer

 D0
D0-D7
D7 : 88-bit
bit data bus used to read or write status,
status command word
or data from or to the 8251A
2. Read/Write Control logic
 Includes
I l d a control t l logic
l i & three
th b ff registers:
buffer it D t register,
Data it
control register & status register.
a
a. Control logic : Interfaces the chip with MPU, MPU determines the
functions of the chip according to the control word in the control
g
register & monitors the data flow.
b. Control Register:16-bit register for a control word consist of two
independent bytes namely mode word & command word.
i. Mode word : Specifies the general characteristics of operation
such as baud, parity, number of bits etc. (fig 2 and 3)
ii. Command word : Enables the data transmission and reception.
c. Status register
 Checks the ready status of the peripheral.
peripheral
 Status word in the status register provides the information concerning
register status and transmission errors.
errors
d. Data register
 Used as an input and output port when the C/D is low

CS C/D WR RD Operation
0 0 1 0 MPU reads data from data buffer
0 0 0 1 MPU writes data from data buffer
0 1 0 1 MPU writes
it a word d tto control
t l register
it
0 1 1 0 MPU reads a word from status register
1 × × × Chip is not selected for any operation
3. Modem Control
The modem control unit handles the modem handshake signals to
coordinate the communication between the modem and the USART.
4 Transmitter section
4.
 Accepts parallel data from MPU & converts them into serial data.
 Has two registers:
g
 Buffer register : To hold eight bits
 Output
p register
g : To convert eight
g bits into a stream of serial bits.
 The MPU writes a byte in the buffer register.
 Whenever the output p register
g is empty;
p y; the contents of buffer
register are transferred to output register.
5. Receiver Section
Accepts serial data on the RxD pin and converts them to parallel data.
data
 Has two registers :
Receiver
Receiver input register
Buffer register
Operating Modes of 8251
1 Asynchronous mode(Txt and Rcv)
1.
2. Synchronous mode(Txt and Rcv)
Asynchronous Mode (Transmission)
 When a data character is sent to 8251A by the CPU, it adds start bits
prior to the serial data bits,
bits followed by optional parity bit and stop bits
using the asynchronous mode instruction control word format. This
sequence is then transmitted using TXD output pin on the falling edge
of TXC.
Asynchronous Mode (Receive)
 The receiver requires only one stop bit to mark end of the data bit
string. The 8-bit character is then loaded into the into parallel I/O
b ff off 8251.
buffer 8251 RXRDY pin i is
i raised
i d high
hi h to
t indicate
i di t to
t the
th CPU that
th t a
character is ready for it.
Synchronous Mode (Transmission)
 The TXD output is high until the CPU sends a character to
8251 which usually is a SYNC character. If the CPU buffer
becomes empty,
empty the SYNC character or characters are inserted
in the data stream over TXD output.

Synchronous Mode (Receiver)

 In this mode,, the character synchronization
y can be achieved
internally or externally. The content of the receiver buffer is
compared with the first SYNC character at every edge until it
matches.
h
8255-Programmable Peripheral Interface
 is a popular interfacing component, that can interface any TTL-
compatible I/O device
de ice to a microprocessor.
microprocessor
 is used to interface to the keyboard and a parallel printer port in PCs
(usually as part of an integrated chipset).
 PPI has 24 pins for I/O that are programmable in groups of 12 pins
and has three distinct modes of operation.
 three i/o ports
 A 8 bits A1 A0 Select
0 0 PA
 B 8 bits
 C 4 bits upper and 4 bits lower 0 1 PB
1 0 PC
1 1 Control reg.
Block Diagram
Data Bus buffer:
 It is a 8-bit bidirectional Data bus.
 Used to interface between 8255 data bus with system bus.
 The
Th direction
di ti off data
d t buffer
b ff isi decided
d id d by
b Read/Control
R d/C t l Logic.
L i
Read/Write Control Logic:
 This
Thi is i getting
i theh input
i signals
i l from
f controll bus
b and
d Address
Add b
bus
 Control signal are RD and WR.
 Address signals are A0,A1,and CS.
 8255 operation is enabled or disabled by CS.
Group A and Group B control:
 Group A and B get the Control Signal from CPU and send the
command to the individual control blocks.
 Group A send the control signal to port A and Port C (Upper) PC7-
PC4.
 G
Group B sendd the
h controll signal
i l to port B and d Port
P C (Lower)
(L )
PC3-PC0.
PORT A:
 This
hi isi a 8-bit
bi buffered
b ff d I/O/ latch.
l h
 It can be programmed by mode 0 , mode 1, mode 2 .
PORT B:
 This is a 8-bit buffer I/O latch.
 It can be programmed by mode 0 and mode 1.
PORT C:
 This is a 8-bit Unlatched buffer Input and an Output latch.
 It is splitted into two parts.
 It can be programmed by bit set/reset operation.
Operation modes:
A. BIT SET/RESET MODE:
 The PORT C can be Set or Reset by sending OUT instruction to the
CONTROL registers.
it
B. I/O Modes
1 MODE
1. O 0(Si
0(Simple i
input / Output):
O )
 Ports A, B, and C can be individually programmed as input or
output
t t portst
 Port C is divided into two 4-bit ports which are independent from
each other
2. MODE 1(Input/output with Hand shake)
 Ports A and B are programmed as input or output ports
 Port C is used for handshaking
3. MODE 2 (bi-directional I/O data transfer)
 Port A is programmed to be bi-directional
 Port C is for handshaking
 Port B can be either input or output in mode 0 or mode 1
 Functions of Control Word.