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INTERRUPT CONTROLLER
Interrupt handling by
CPU vs. 8259
Why 8259A ??
• 8085 Processor has only 5 hardware interrupts to handle a
maximum of 5 I/O devices.
(RST 7.5, RST6.5, RST 5.5, INTR, TRAP)
IMR
• This register can be programmed by an OCW to store
the bits which mask specific interrupts.
• The master puts out the identification code to select one of the slave
from 8 slaves through these pins.
• The slave thus selected puts out the address of ISR during second
and third interrupt acknowledge pulses from the CPU.
Interrupt Sequence
Following events occur:
1) One or more interrupt request lines(IR0-IR7) are raised high.
2) Priority resolver checks for the 3 register and sets INT high.
3) In response to INTR signal 8085 mp sends an INTA pulse.
4) Upon receiving INTA from 8085, corresponding IRR line(IR0-
IR7) is reset.
4) 8259 places the opcode for call instruction.
5) Call instruction initiates two more interrupt acknowledge
cycles.
6) During the two interrupt acknowledge cycles, 8259 places the
lower byte of ISR and higher byte of ISR address.
7) When interrupt cycle is completed an EOI command is issued
by the microprocessor.
8259A- OPERATING MODES
FULLY NESTED MODE:
• General purpose mode / default mode.
• IR0 to IR7 are arranged from highest to lowest.
• IR0 Highest IR7Lowest