Jeff Shannon for EET 445 The Functions of the 8085A
• Is an 8-bit microprocessor that can access
up to 64K (65,536) bytes of memory. • It performs clock generation, system bus control, interrupt priority selection, and execution of the instruction set. • Can address 256 I/O locations (00-FF), but IO/M from CPU distinguishes it. Registers of the 8085 • Accumulator (8-bit) • Program Counter (16-bit) • General purpose (BC, DE, and HL) (6 8- bit or 3 16-bit) registers • Stack Pointer • Flag Register • Carry flag (CY)- Acts as a ninth MSB for the accumulator • Auxiliary Carry Flag (AC)- Represents overflow from bit 3 of ACCA. Used for BCD • Sign Flag (S)- Looks at bit 7 of ACCA and is set in correspondence with bit 7. • Zero Flag (Z)- Set when the contents of ACCA are zero. • Parity Flag (P)- sets if parity of ACCA is even, if odd parity it is cleared. Internal Clock generator
• Only needs a quartz crystal OR an
external clock input at X1
• Crystal- 6.25 MHz
• CLK is half the frequency of the crystal input signal 5 Interrupt types for the 8085 • INTR- a maskable interrupt that can be enabled/disabled with the EI or DI software instructions (lowest priority) • RST 5.5, 6.5, 7.5- RST 5.5 and 6.5 are level sensitive (they acknowledge when held high), 7.5 is edge-triggered--signal is sent to the RST 7.5 flip-flop (5.5 has 4th priority & 7.5 has second) • TRAP-highest priority and unmaskable. Rising edge triggers but must be held high to be received internally. Serial Input and Output • When a RIM (read int-masks) occurs, the status of SID pin is read into ACCA. (INPUT) • When a SIM (set int-masks) occurs, bit 7 of ACCA is loaded out of the SOD output, as long as bit 6 of ACCA is high Multiplexed Bus Cycle Timing
• Fetch and Execute phases of direct STA
instruction State Transition Sequence
• The machine cycles are equivalent to 3 cycles
of CLK output, except for the opcode fetch machine cycle which will normally contain 4 to 6 CLK cycles Opcode Fetch Machine Cycle 8085A Pinout Thanks for Your Attention