Lecture 3

INTEL 8085
MICROPROCESSOR
HARDWARE
ARCHITECTURE
Dr. Marwa Gamal
 8085
 The 8085 has been one of the popular
microprocessors of its time
 The 8085 removed certain architectural
disadvantages of its predecessor, the 8080

8085 8080
Power supply a single +5 V power against three power
supply supply lines
Clock signal a single clock signal two clock signals
Pulse width 320 ns pulse width 500 ns pulse
others on-chip serial I/O --------------
capability as
well as interrupt request
pins for hardware
HARDWARE ARCHITECTURE
HARDWARE ARCHITECTURE
The 8085 Clock
An external crystal or R-C network can be
connected between X1 and X2
Programmable Registers
 There is one 8-bit accumulator
(abbreviated ACC or A register), and six 8-
bit general-purpose registers
 It is also possible to use these registers in
pairs to store 16-bit information.
 The stack pointer (SP) is a 16 bit register
which points to the location of the top of
the stack.
 The program counter (PC) is a 16-bit
register which points to the next instruction
to be executed.
Programmable Registers
 both these registers (SP and PC) contain
memory addresses,
 there is a 16-bit register called the
Program Status Word (PSW).
 The higher-order 8 bits of PSW contain
Accumulator contents and the lower-order 8
bits have the following five condition flags:(
ZERO (Z)-SIGN (S)-PARITY (P)-CARRY
(CY)- AUX. CARRY (AC)
 Address and Data Buses
 Has 16 address lines and 8 data lines
 The 8085 outputs an Address Latch
Enable (ALE) signal which
indicates the presence of
address on AD0–AD7.
The falling edge of ALE is
used to latch the address
present on lower-order
address lines AD0– AD7
Memory Interfacing
 8085 has 16 address lines
 The 8085 will have to issue Read and
Write control signals
 there is the necessity to have a signal that
informs us as to whether these address
lines contain data or address.
 decoding the address bits and determining
the chip where the specified memory
address is located.
Memory Interfacing Read control signal
Write control signal
IO/M Control signal
Memory Interfacing
 Slow memory or I/O devices can gain
additional time of the 8085 by inputting the
READY signal. The 8085 waits till this
signal is withdrawn and then performs the
normal operation. This signal is also
referred as Wait State Request signal
Direct Memory Access
 Two signals are associated with Direct
Memory Access—HOLD and HLDA.
 HOLD is used for DMA request.
 The CPU sends HLDA to acknowledge to
device that HOLD request has been
received
Serial Input–Output
 Two lines( Serial Input Data (SID) and Serial
Output Data (SOD).
 SID line is used by the serial output devices
to send bit serial data to processor and SOD
is used by the processor to output bit serial
data to serial input devices.
 Two software instructions
 RIM (Read Interrupt Mask) transfers the bit information
present on the SID line to the seventh bit of ACC
 SIM (Set Interrupt Mask) transfers the seventh bit of ACC
to SOD line
The 8085 Activity Status Information
•Two signals S0 and S1 define the activity on the buses as
follows.
The 8085 Reset
 Two signals are associated with the reset
logic.
 RESET IN input signal, when goes low,
resets the processor. The program
counter is set to zero, and interrupt enable
and HLDA flip-flops are reset.
 The CPU outputs the RESET OUT signal
which is synchronized with the clock. It
may be used to reset the other associated
circuits.
THE 8085 PIN OUT
 The 8085 microprocessor is available on a
40-pin Dual-in-Line Package (DIP).