LOGIC II

Counters & Register

Lecture 4

Dr. Marwa Gamal

 Displaying the contents
 Connecting the output of each FF to a small
indicator LED
The indicator LED method becomes
inconvenient as the size (number of bits) of the
counter increases because it is much harder to
decode the displayed results mentally.
 Electronically decoding is preferable method
Active-HIGH Decoding
 A MOD-X counter has X different states
 A decoding network is a logic circuit that
generates X different outputs.

 Using AND Gates for decoding

To Decode a MOD-8 Counter
(produce pulse at specific count)

Active-LOW Decoding
 Using NAND Gates for decoding
Active-HIGH Decoding
 How many AND gates are required to decode
completely all of the states of a MOD-32 binary
counter?

• What are the inputs to the gate that decodes for

the count of 21 (that is,101012)?
 by predicting the FF control inputs for
each state of the counter

Steps of Analysis process

1) write the logic expression for each FF control

input.
2) Assume a PRESENT state for the counter
3) Apply that combination of bits (PRESENT state
) to the control logic expressions.
4) The outputs from the control expressions will
allow us to predict NEXT state
5) Repeat the analysis process until the entire
count sequence is determined.
EXAMPLE:

1) Control expression

2) Assume a PRESENT state = 0000

3 & 4 ) Apply PRESENT state and find NEXT
state
Steps of design

1) Determine the desired

number of bits (FFs) and the
desired counting

2) Draw the state transition

diagram showing all possible
states, including those that
are not part of the desired
3) Use the state transition
diagram to set up a table
that lists all PRESENT
states and their NEXT
states.
4) Add a column for each JK input (or other
inputs). Indicate the level required at each J
and K in order to produce transition to the
NEXT state.
5) Implement the final expressions (obtained from the K
map).
6) Design the logic circuits needed to generate the levels
required at each J and K input..
Steps of design
1) Determine the desired number of bits (FFs) and
the desired counting
2) Draw the state transition diagram showing all
possible states, including those that are not part
of the desired
3) Use the state transition diagram to set up a
table that lists all PRESENT states and their
NEXT states.
4) Add a column for each JK input in order to
produce transition to the NEXT state.
5) Implement the final expressions (obtained from
the K map).
6) Design the logic circuits needed to generate
the levels required at each J and K input..
 Example:
MOD-5 Counter Using D-type Flip-Flops
 Example:
MOD-5 Counter Using D-type Flip-Flops
Registers can be classified by the way
data is entered for storage, and by the
way data is outputted from the
register.

– Parallel in/parallel out (PIPO)

– Serial in/serial out (SISO)
– Parallel in/serial out (PISO)
– Serial in/parallel out (SIPO)
A six-bit register
 parallel inputs(synchronous)
on the PGT of the clock input
CP (D5 through D0) and parallel
outputs Q5 through Q0.
MR (Master Reset) to reset
asynchronously all of the FFs
 eight-bit shift register
data loaded into it one bit
at a time in the same order.
 QH is accessible
serial data is input on
SER and will be stored in
FF QA
The serial output is
obtained at QH
asynchronous clear input (CLR) and
synchronous (SH/LD) .
The synchronous (SH/LD) can be inhibited
(disabled) by applying a HIGH to the CLK INH
8 bit register
– Serial data entry via
DS
–Asynchronous
parallel data entry P0
through P7
– Only the outputs of
Q7 are accessible
• CP is clock input for
shifting
• CP INH ORed with
CP
• Shift load input
Example : 74HC165 PISO Waveforms
Ds = 0, CP INH = 0, Output values for given inputs
(P0=P7)
8 bit shift register A and B inputs are
• Each FF output combined in an AND
is externally gate for serial input.
accessible.
• Shift occurs on
PGT of the clock
input.
Last FF shifts its value to first FF
Uses D-type FFs (JK FFs can also be
used)
it is made to circulate as clock pulses are
applied.
it is called a ring counter.
Must start with only one FF in the 1state
and all others in the 0 state.
a MOD-N ring counter uses N flip-flops
a MOD-8 ring counter requires eight FFs,
while a MOD-8 binary counter requires only
three.
Johnson counter:
• Also called a twisted ring counter
• Same as ring counter but the inverted
output of the last FF is connected to
input of the first FF
•The MOD number of a Johnson
counter will always be equal to twice
the number of FFs
Choose
If a 10-bit ring counter has an initial state 1101000000,
what is the state after the second clock pulse?
a) 1101000000
b) 0011010000
c) 1100000000
d) 0000000000

What is the preset condition for a ring shift counter?

a) All FFs set to 1
b) All FFs cleared to 0
c) A single 0, the rest 1
d) A single 1, the rest 0
 Ring shift and Johnson counters are ____________
a) Synchronous counters
b) Asynchronous counters
c) binary counters
d) Synchronous and binary counters
In a parallel in/parallel out shift left
register, D0 = 1, D1 = 1, D2 = 1, and D3 =
0. After three clock pulses, the data
outputs are ________
a) 1110
b) 0001
c) 1100
d) 1000
Thank you!!!
Chapter 7
Ends!!!