INTEL 8085 MICROPRCESSOR

8085 Specifications
 Introduced March 1976

 Clock rate 3 MHz

 0.37 MIPS

 Bus width 8 bits data, 16 bits address

 Number of transistors 6,500 at 3 μm

 Binary compatible downwards with the 8080.

 Used in Toledo scales.

 Also was used as a computer peripheral controller – modems, hard disks, printers,
 8085 Pins
 For complete understanding of the interfacing circuits of
memory, I/O devices etc. to the 8085 CPU it is required to learn
about the functions of all the pins of 8085.
 The pins of 8085 are classified in following groups:
 Address and Data pins
 Control & status pins
 Interrupt pins
 Serial I/O pins
 Clock pins
 Reset pins
 DMA pins
 Power supply pins
 8085 Architecture

 To develop programs for 8085, it is required to completely understand

the internal functional blocks of 8085.

 8085 architecture includes following functional blocks:

 8085 Registers

 Timing and control unit

 ALU

 Interrupt control unit

 Serial I/O control unit

 Instruction decoder & encoder unit

 Programming 8085

 Programming of 8085 requires complete knowledge of the

instruction set and its structure.

 This requires study of:

 8085 Instruction set

 8085 addressing modes

 One, two & three bytes instruction

 Programming examples
 8085 Pin configuration
 40 pin device
8085 Bus Architecture
 8085 Pin Description
 Higher Order Address pins- A15 – A8

 Lower Order Address/ Data Pins- AD7-AD0

 These are time multiplexed pins and are de-multiplexed using the pin ALE

 Control Pins – RD, WR

 These are active low Read & Write pins

 Status Pins – ALE, IO/M (active low), S1, S0

 ALE (Address Latch Enable)-Used to de-multiplex AD7-AD0

 IO/M – Used to select I/O or Memory operation

 S1,S0 – Denote the status of data on data bus

 8085 Pin Description
 S1,S0 – Denote the status of data on data bus
S1 S0 OPERATIONS

0 0 HALT

0 1 WRITE

1 0 READ

1 1 FETCH
 8085 Pin Description
 Control Pins – RD, WR
 These are active low Read & Write pins
 RD – used to control READ operation of the microprocessor
 When this pin goes low, the microprocessor reads the data from
memory or I/O device
 WR – controls the write operations of the microprocessor
 When this pin goes low, data is written to memory or I/O device
 8085 Pin Description
IO/M – Used to select I/O or Memory operation

 Consider an address to be processed

 Address can be of a memory or I/O function

 Thus IO/M is used to specify the address destination

 When the pin goes high, the address is for an I/O device.

 When the pin goes low, the address is assigned for memory
 8085 Pin Description
 Interrupt Pins
 TRAP,
 RST7.5,
 RST 6.5,
 RST 5.5,
 INTR,
 INTA

 These are hardware interrupts used to initiate an interrupt

service routine stored at predefined locations of the
system memory.
 8085 Pin Description
 Serial I/O pins – SID (Serial Input Data), SOD (Serial Output
Data).
 These pins are used to interface 8085 with a serial device.
 8085 Pin Description
 Clock Pins- X1, X2, CLK(OUT)
 X1, X2- These are clock input pins.
 A crystal is connected between these pins such that fcrystal=
2f8085

 fcrystal= crystal frequency

 f8085 = operating frequency of 8085

 CLK(OUT) – This is an auxiliary clock output source

 Reset Pins – Reset In (active low), Reset Out

 Reset In is used to reset 8085 whereas Reset Out can be used to
reset other devices in the system
 8085 Pin Description
 DMA (Direct Memory Access) pins – HOLD,
HLDA
 These pins are used when data transfer is to be
performed directly between an external device
and the main memory of the system.

 Power Supply Pins - +VCC, VSS

 8085 Pin Description
 HOLD
 Indicates if any device is requesting the use of address or data bus.

 Device requests use of the buses by giving HOLD signal

 Take an example of two peripheral devices, LCD and ADC

 Suppose ADC is using address and data bus, and if LCD requests
use of address and data bus by giving HOLD signal

 Microprocessor will transfer control to LCD as soon as current

cycle is over

 After LCD process is over, control is transferred back to ADC.

 8085 Pin Description
 HLDA

 Is the acknowledgement signal for HOLD

 It indicates whether the HOLD signal is received or

not

 After the execution of HOLD request, HLDA goes

low
 8085 Pin Description
 READY

 Used by microprocessor to check whether a peripheral is

ready to transfer or accept data

 Peripherals e.g. LCD, ADC etc.

 The peripherals are connected to microprocessor using

READY pin

 If READY is high then the peripheral is ready for data transfer

8085 Internal Architecture
 8085 Internal Architecture
The Registers are of 8-bit & 16-bit size used for different
purposes.

 A- Accumulator – This is an special purpose register.

 All the ALU operations are performed with reference to the contents
of Accumulator.

 B,C,D,E,H,L – General purpose registers.

 These registers can also be used for 16-bit operations in pairs.

 The default pairs are BC, DE & HL.

 8085 Internal Architecture
 F – Flag register – This register indicates the status of the ALU
operation.

 PC – Program Counter – This is a 16-bit register used to address the

memory location from where an instruction is going to be executed.

 SP – Stack pointer - This is a 16-bit register used to address the

top of the stack memory location.

 Temporary register, W & Z – These registers are only used by 8085

and are not available for the programmer.
 8085 Internal Architecture
ALU – Arithmetic & Logic Unit

 ALU of 8085 performs 8-bit arithmetic & logical

operations.

 The operations are generally performed with Accumulator

as one of the operands.

 The result is saved in accumulator register.

 8085 Internal Architecture
Timing & Control Unit

 This unit works as the brain of the CPU.

 generates all the timing and control signals to perform all

the internal & external operations of the CPU.
 8085 Internal Architecture
Instruction Decoder & Machine Cycle Encoder Unit

 This unit decodes the op-code stored in the Instruction

Register (IR)

 encodes it for the timing & control unit to perform the

execution of the instruction.
 Flag Register
 8 bit register –shows the status of the
microprocessor before/after an operation.
 S (sign flag),

 Z (zero flag),

 AC (auxillary carry flag),

 P (parity flag) &

 CY (carry flag)
 Flag Register

D7 D6 D5 D4 D3 D2 D1 D0

S Z X AC X P X CY
 Flag Register
Sign Flag

 Used for indicating the sign of the data in the accumulator.

 The sign flag is set if negative (1 –negative)

 The sign flag is reset if positive (0 –positive)

 Flag Register
Zero Flag

 Is set if result obtained after an operation is 0

Carry Flag

 Is set if there is a carry or borrow from arithmetic operation

 Flag Register
Auxillary Carry Flag–

 Is set if there is a carry out of bit 3.

Parity Flag

 Is set if parity is even

 Is cleared if parity is odd

 Program Counter (PC)
 This is a register that is used to control the sequencing of the execution of
instructions.

 This register always holds the address of the next instruction.

 Since it holds an address, it must be 16 bits wide.

 Stack Pointer (SP)
 The stack pointer is also a 16-bit register that is used to point into memory.

 The memory this register points to is a special area called the stack.

 The stack is an area of memory used to hold data that will be retrieved
soon.

 The stack is usually accessed in a Last In First Out (LIFO) fashion.

 Instruction Register (IR) and Decoder
 Instruction is stored in IR after fetched by processor

 Decoder decodes instruction in IR

 8085 Bus Architecture
 System Bus –wires connecting memory & I/O to microprocessor
1. Address Bus
 Unidirectional

 Identifying peripheral or memory location

2. Data Bus
 Bidirectional

 Transferring data

3. Control Bus
 Synchronization signals

 Timing signals
 Control signal
 8085 Address and Data Buses
 The address bus has 8 signal lines A8 –A15 which are unidirectional.

 The other 8 address bits are multiplexed(time shared) with the 8 data bits.

 So, the bits AD0 –AD7are bi-directional and serve as A0 –A7and D0 –

D7at the same time.

 During the execution of the instruction, these lines carry the address bits
during the early part, then during the late parts of the execution, they
carry the 8 data bits.

 In order to separate the address from the data, we can use a latch to save
the value before the function of the bits changes.
 8085 Address and Data Buses
 Thus, AD7–AD0 lines are serving a dual purpose and they need to be
demultiplexed to get all the information.

 The high order bits of the address remain on the bus for three clock periods.
However, the low order bits remain for only one clock period and they would be
lost if they are not saved externally.

 Also, notice that the low order bits of the address disappear when they are
needed most.

 To make sure we have the entire address for the full three clock cycles, we will
use an external latch to save the value of AD7–AD0 when it is carrying the
address bits.

 We use the ALE signal to enable this latch.

8085 Address and Data Buses
 8085 Address and Data Buses

 Given that ALE operates as a pulse during T1, we will be able

to latch the address.

 Then when ALE goes low, the address is saved and the AD7–
AD0 lines can be used for their purpose as the bi-directional
data lines.
 8085 Address and Data Buses

 The high order address is placed on the address bus and hold for
3 clk periods,

 The low order address is lost after the first clk period, this address
needs to be hold however we need to use latch

 The address AD7 –AD0 is connected as inputs to the latch

74LS373.

 The ALE signal is connected to the enable (G) pin of the latch
and the OC –Output control –of the latch is grounded.
8085 Address and Data Buses
 Assignment 1

 1. Using clearly labelled diagrams, explain on the

multiplexing and de-multiplexing principle on address and
data lines of the intel8085 microprocessor. Include all the
timing diagrams [20]
END OF SLIDESHOW

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