Computer Architecture

Course Code : CCE-3509

INPUT-OUTPUT
ORGANIZATION

Mohammad Nadib Hasan

Asst. Lecturer
Department of CCE
 Highlights

§ Peripheral Devices
§ Input-Output Interface
§ Asynchronous Data Transfer
§ Modes of Transfer
§ Priority Interrupt
§ Direct Memory Access
§ Input-Output Processor
§ Thunderbolt and Infinite Band

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 Peripheral Devices
vInput Devices:
§ Keyboard
§ Screen Input Devices
§ Optical input devices • Touch Screen
• Card Reader • Light Pen
• Paper Tape Reader • Mouse
• Bar code reader § Analog Input Devices
• Digitizer
• Optical Mark Reader
§ Magnetic Input Devices
• Magnetic Stripe Reader
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 Peripheral Devices
vOutput Devices:
§ Card Puncher, Paper Tape Puncher
§ CRT
§ Plotter
§ Analog
§ Voice
§ Printer (Impact, Ink Jet,
• Laser, Dot Matrix)

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 Input-Output Interface
§ Provides a method for transferring information between internal storage (such as
memory and CPU registers) and external I/O devices
§ Resolves the differences between the computer and peripheral devices
• Peripherals - Electromechanical Devices
• CPU or Memory - Electronic Device
• Data Transfer Rate
• Peripherals - Usually slower
• CPU or Memory - Usually faster than peripherals
• Some kinds of Synchronization mechanism may be needed
• Unit of Information
• Peripherals – Byte, Block, …
• CPU or Memory – Word
• Data representations may differ
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 I/O BUS AND INTERFACE MODULES
I/O bus
Data
Processor Address
Control

Interface Interface Interface Interface

Keyboard
and Printer Magnetic Magnetic
display disk tape
terminal

vEach peripheral has an interface module associated with it

§ Interface
• Decodes the device address (device code)
• Decodes the commands (operation)
• Provides signals for the peripheral controller
• Synchronizes the data flow and supervises
• The transfer rate between peripheral and CPU or Memory
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 I/O BUS AND INTERFACE MODULES
§ There are 4 types of command that an interface may receive.
1.Control Command:
• Rewind the magnetic tap
• To start moving magnetic tap in forward direction.
2.Status command:
• Used to test various status condition in interface and peripheral.
3.Data output command:
• Cause the interface to respond by transferring data from bus into one of its register.
4.Data Input command:
• Opposite of Data output command

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 I/O BUS AND MEMORY BUS
§ Functions of Buses:
• MEMORY BUS is for information transfers between CPU and the MM

• I/O BUS is for information transfers between CPU and I/O devices through
their I/O interface

• Three ways to communicate processor bus with memory bus and I/O bus
1. Use two separate buses, one for memory and the other for I/o
2. Use one common bus but separate control lines for each function
3. Use one common bus with common control lines for both functions

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 ISOLATED vs MEMORY MAPPED I/O
§ Isolated I/O:
• Separate I/O read/write control lines in addition to memory read/write control lines
• Separate (isolated) memory and I/O address spaces
• Distinct input and output instructions
• Memory-mapped I/O:
• A single set of read/write control lines
(no distinction between memory and I/O transfer)
• Memory and I/O addresses share the common address space
-> reduces memory address range available
• No specific input or output instruction
-> The same memory reference instructions can be used for I/O transfers
• Considerable flexibility in handling I/O operations
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 Virtual memory
§ .. Port A I/O data
register
Bidirectional Bus
data bus buffers
Port B I/O data
register

Internal bus
Chip select CS
Register select RS1 Control Control
Timing register
Register select RS0 and
I/O read Control
RD Status Status
I/O write WR register

CS RS1 RS0 Register selected

0 x x None - data bus in high-impedence
1 0 0 Port A register
1 0 1 Port B register
1 1 0 Control register
1 1 1 Status register

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 ASYNCHRONOUS DATA TRANSFER
§ Synchronous and Asynchronous Operations:
• Synchronous: All devices derive the timing information from common clock line.
• Asynchronous: No common clock.
• Asynchronous Data Transfer:
Asynchronous data transfer between two independent units requires that
control signals to be transmitted between the communicating units.

§ Two Asynchronous Data Transfer Methods:

• Strobe pulse
• Handshaking

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 STROBE CONTROL
§ Employs a single control line at the time each transfer
§ The strobe may be activated by either the source or the destination unit
Source-Initiated Strobe Destination-Initiated Strobe
for Data Transfer for Data Transfer

Block Diagram Block Diagram

Data bus Data bus
Source Destination Source Destination
unit Strobe unit unit Strobe unit

Timing Diagram Timing Diagram

Valid data Valid data
Data Data

Strobe Strobe

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 HANDSHAKING
§ Dis advantage of Strobe Method:

• Source-Initiated: The source unit that initiates the transfer has no way of knowing
whether the destination unit has actually received data.

• Destination-Initiated: The destination unit that initiates the transfer no way of

knowing whether the source has actually placed the data on the bus

§ To solve this problem, the HANDSHAKE method introduces a one more signal i.e
acknowledge signal to provide a Reply to the unit that initiates the transfer.

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 SOURCE-INITIATED TRANSFER USING HANDSHAKE
Data bus
§. Source Data valid Destination
Block Diagram unit Data accepted unit

Valid data
Data bus
Timing Diagram

Data valid

Data accepted

Sequence of Events Source unit Destination unit

1. Place data on bus.
2. Enable data valid.
3. Accept data from bus.
4. Enable data accepted
5. Disable data valid.
6.Invalidate data on bus.
7. Disable data accepted.
8. Ready to accept next
Data (initial state).

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 DESTINATION-INITIATED TRANSFER USING
HANDSHAKE
Data bus
§. Block Diagram Source Data valid Destination
unit Ready for data unit

Timing Diagram Ready for data

Data valid

Valid data
Data bus

Sequence of Events Source unit Destination unit

Ready to accept data.
Place data on bus. Enable ready for data.
Enable data valid.

Accept data from bus.

Disable data valid. Disable ready for data.
Invalidate data on bus
(initial state).

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 HANDSHAKING
§ Handshaking provides a high degree of flexibility and reliability because the
successful completion of a data transfer relies on active participation by both
units.
§ If one unit is faulty, data transfer will not be completed
-> Can be detected by means of a timeout mechanism

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 ASYNCHRONOUS SERIAL TRANSFER
§ Employs special bits which are inserted at both ends of the character code
§ Each character consists of three parts; Start bit; Data bits; Stop bits.

1 1 0 0 0 1 0 1

Start Stop
Character bits
bit bits
(1 bit) (at least 1 bit)

§ Rules for Transmission:

• When data are not being sent, the line is kept in the 1-state (idle state)
• The initiation of a character transmission is detected by a Start Bit , which is generally 0.
• The character bits always follow the Start Bit
• After the last character , a Stop Bit is detected when the line returns to the 1-state for at least
1 bit time.
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 Asynchronous Serial Communication Vs
Synchronous Serial Communication
.
Sr.No. Asynchronous Serial Communication
1 Transmitter and receiver are not
synchronous by clock
2 Bit of data are transmitted at constant rate.
Synchronous Serial Communication
Transmitter and receiver are synchronous
by clock
Data bits are transmitted with synchronous
of clock.

3 Data transfer is character oriented Data transfer takes place in block

4 Start and stop bits require for each Start and atop bits are not require
character
5 Used in low speed transmission less than 20 Used in high speed transmission
kbits/sec

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 MODES OF TRANSFER
• 3 different Data Transfer Modes between the central computer (CPU or Memory) and
peripherals -
1. Program-Controlled I/O
2. Interrupt-Initiated I/O
3. Direct Memory Access (DMA)

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 MODES OF TRANSFER : Program-Controlled I/O
§. Program-Controlled I/O
Data bus Interface I/O bus
Address bus Data register
Data valid I/O
CPU I/O read device
I/O write Status Data accepted
register F

Read status register

Check flag bit

=0 Polling or Status Checking

flag
=1 • Continuous CPU involvement
Read data register
• CPU slowed down to I/O speed
Transfer data to memory • Simple
• Least hardware
no Operation
complete?
yes
Continue with
program

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 MODES OF TRANSFER : Interrupt Initiated I/O
§ Interrupt Initiated I/O:
• I/O interface, instead of the CPU, monitors the I/O device.
• When the interface determines that the I/O device is ready for data
transfer, it generates an Interrupt Request to the CPU.
• Upon detecting an interrupt, CPU stops momentarily the task it is doing,
branches to the service routine to process the data transfer, and then
returns to the task it was performing.

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 MODES OF TRANSFER : DMA (Direct Memory Access)

§ DMA (Direct Memory Access):

• Large blocks of data transferred at a high speed to or from high speed
devices, magnetic drums, disks, tapes, etc.
• DMA controller: Interface that provides I/O transfer of data directly to
and from the memory and the I/O device.
• CPU initializes the DMA controller by sending a memory address and the
number of words to be transferred.
• Actual transfer of data is done directly between the device and memory
through DMA controller
-> Freeing CPU for other tasks

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 DIRECT MEMORY ACCESS (DMA)
§ Block of data transfer from high speed devices, Drum, Disk, Tape
§ DMA controller - Interface which allows I/O transfer directly between Memory and
Device, freeing CPU for other tasks
§ CPU initializes DMA Controller by sending memory address and the block size(number of
words)
CPU bus signals for DMA transfer


ABUS Address bus High-impedence
Bus request BR DBUS Data bus (disabled)
CPU when BG is
Bus granted BG RD Read
WR Write enabled

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 DIRECT MEMORY ACCESS (DMA)
§ Block diagram of DMA controller:

Address bus

Data bus Data bus Address bus

buffers buffers

Internal Bus
DMA select DS Address register
Register select RS
Read RD Word count register
Write WR Control
logic
Bus request BR Control register

Bus grant BG
Interrupt Interrupt DMA request
DMA acknowledge to I/O device

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 DMA I/O OPERATION
§ Starting an I/O: CPU executes instruction to
1. Load Memory Address Register (The starting address of memory word)
2. Load Word Counter (No. of words in memory block)
3. Load Function(Read or Write) to be performed
4. Issue a GO command
• Upon receiving a GO Command DMA performs I/O operation as follows independently
from CPU
§ Input:
[1] Input Device <- R (Read control signal)
[2] Buffer(DMA Controller) <- Input Byte; and
assembles the byte into a word until word is full
[4] M <- memory address, W(Write control signal)
[5] Address Reg <- Address Reg +1; WC(Word Counter) <- WC - 1
[6] If WC = 0, then Interrupt to acknowledge done, else go to [1]
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 DMA I/O OPERATION
§ Output:
[1] M R<- M Address, M Address R <- M Address R + 1, WC <- WC - 1
[2] Disassemble the word
[3] Buffer <- One byte; Output Device <- W, for all disassembled bytes
[4] If WC = 0, then Interrupt to acknowledge done, else go to [1]
 DMA TRANSFER
§.
Interrupt
Random-access
BG
CPU memory unit (RAM)
BR
RD WR Addr Data RD WR Addr Data
Read control
Write control
Data bus
Address bus

Address
select

RD WR Addr Data
DS DMA ack.

RS DMA I/O
Controller Peripheral
BR device
BG DMA request
Interrupt
 CYCLE STEALING
§ Memory Bus Controller:
• Coordinating the activities of all devices requesting memory access
• Priority System
Memory accesses by CPU and DMA Controller are inte, with the top priority given to DMA
Controller.
§ Cycle Steal
• CPU is usually much faster than I/O(DMA), thus CPU uses the most of the memory
cycles.
• DMA Controller steals the memory cycles from CPU
• For those stolen cycles, CPU remains idle
 INPUT/OUTPUT PROCESSOR
§.

Central
processing
unit (CPU)
Peripheral devices

Memory Bus
Memory
unit PD PD PD PD

Input-output
processor
I/O bus
(IOP)
 CPU / CHANNEL (IOP) COMMUNICATION
§. CPU operations IOP operations
Send instruction
to test IOP.path
Transfer status word
to memory
If status OK, then send
start I/O instruction
to IOP. Access memory
for IOP program

CPU continues with

another program Conduct I/O transfers
using DMA;
Prepare status report.

I/O transfer completed;

Interrupt CPU
Request IOP status

Transfer status word

Check status word to memory location
for correct transfer.

Continue
 THANKS MUCH

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