Chapter 11 - Part1

4/11/22
Chapter 11: Basic I/O Interface
Objectives
• Operation of basic I/O operations
• Decode 8 and 16-bit addresses for enabling I/O ports
• Handshaking for I/O operations
• Interface and program the 82C55 PPI (programmable
peripheral interface)
• Using the 82C55 to connect LEDs, keyboards, etc. to
the processor
• Interface stepper and DC motors to the processor
• Interface and program the 16550 programmable
asynchronous serial interface adapter (UART)
• Interface and program the 8254 programmable
interval timer (PIT)
Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 2
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4/11/22
11–1 INTRO TO I/O INTERFACE

• I/O instructions (IN, INS, OUT, and OUTS) are
explained.
• Also isolated (direct or I/O mapped I/O) and memory-
mapped I/O, the basic input and output interfaces,
and handshaking.
• IN and OUT instructions:
– The IN instruction (I/O Read): Inputs data from an
external I/O device to the accumulator.
– The OUT instruction (I/O Write): Copies the
contents of the accumulator out to an external I/O
device
I/O Address
• I/O devices have I/O addresses (I/O ports)
• Up to 64K I/O bytes can be addressed
• The 16-bit port address appears as A15-A0
Ø This allows I/O devices at addresses 0000H-FFFFH
• Two ways to specify an I/O port address:
- An 8-bit immediate (fixed) address:
IN AX, Port_8 ; Reads a word from port Port_8
0000H-00FFH (can only see the first 256 addresses)
- A 16-bit address located in register DX :
OUT DX, AL; outputs the byte in AL to the port whose
address is in DX
Ø 0000H-FFFFH (upto 64K addresses).
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4/11/22
e a d
DX
DX
I /O R
DX
r ite
I /O W
Figure 11–1 The memory and I/O maps for the 8086/8088 microprocessors. (a)
Isolated I/O. (b) Memory-mapped I/O.
– in the PC, isolated I/O

ports are used to control
peripheral devices
– an 8-bit port address is
used to access devices
located on the system
board, such as the timer
and keyboard interface
– a 16-bit port is used to
access serial and parallel
ports, video and disk drive
systems
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Isolated vs. Memory Mapped

• I/O can be either:
– Isolated I/O: uses the dedicated I/O instructions (IN, OUT
and INS, OUTS) and has its own address space for I/O
ports (0000H-FFFFH)- isolated from the memory address
space
– Memory mapped I/O: uses memory reference instructions ,
e.g. MOV, and a region of the memory address map. So
address space is shared between memory and I/O (used
by only one of them) MOV AL,[0008]
§ Both techniques can be used with Intel processors,
but most Intel-based systems e.g. the PC, use
isolated I/O
Ø Some other processors do not have dedicated I/O
instructions and therefore use only memory-mapped
I/O addressing, e.g. the PowerPC microprocessor
(Macintosh computers)
• A disadvantage of isolated I/O is that data transferred

between I/O and microprocessor must be accessed
by the IN, INS, OUT, and OUTS instructions.
• Advantage of Memory Mapped I/O is any memory
transfer instruction can access the I/O device.
• Disadvantage is a portion of memory system is used
as the I/O map.
– reduces memory available to applications
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The PC I/O space

• The PC I/O space mainly exists at locations below
I/O port 0400H
• Main board devices appear at addresses 0000H
through 00FFH
• Early I/O devices appear at I/O locations 0100H
through 03FFH
• Modern components appear at I/O locations above
0400H
The PC I/O
Address Space
03FF Must use 16-bit variable

I/O address in register DX
Reserved for use by

system components
and ISA bus 0100
00FF
On Board Devices
Can Use either:

Interval (8254) - Fixed (immediate) 8-bit
I/O address in instruction, p8
- Variable 16-bit
I/O address in register DX
0000 0000
10
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IN (I/O Read) & OUT (I/O Write)

• The IN instruction primarily takes he following forms:
IN AL,23H ;immediate
IN AL,DX ;DX holds address
IN AX,44H
IN AX,DX
IN EAX,2AH
IN EAX,DX
• The OUT instruction primarily takes the following forms:
OUT 23H,AL ;immediate

OUT DX,AL ;DX holds port
OUT 4CH,AX
OUT DX,AX
OUT 1EH,EAX
OUT DX,EAX
11
Basic Input Port (for I/O Reads)
• The basic input port connects an external set of bits

to the µP data bus whenever the µP executes the
correct IN instruction with the correct I/O port
address
• External device puts data on the µP data bus
à Must include a 3-state (Tri-State) buffer to limit

access to the processor data bus to the duration of
executing the I/O instruction only
12
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Figure 11–3 The basic input interface illustrating the connection of eight switches.
Note that the 74ALS244 is a three-state buffer that controls the application of the
switch data to the data bus.
Pull-up
Resistors
To µP
The SEL signal is generated (active low) 3-state buffer

By decoding: Circuit can be expanded for
- The address for the I/O port 16-bit (word) or 32-bit (DWord)
- The I/O READ operation interfaces
13
Basic Output Port (for I/O Writes)

• The basic output port writes data from the µP data
bus to an output port whenever the µP executes the
correct OUT instruction with the correct I/O port
address
• Must latch the processor data on the bus during the
I/O instruction to make it available indefinitely for the
port
• No need for 3-state (Tri-State) buffers as the data
bus at the input side of the latch
14
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Figure 11–4 The basic output interface connected to a set of LED displays.
Circuit can be expanded for

16-bit (word) or 32-bit (DWord)
interfaces
From µP
Data is latched and remains until the next OUT

instruction to this port is executed
15
5 x8 Dot Matrix Example
Org 100H
.DATA
Dots DB 01111111b, 01001001b, 01001001b, 01001001b, 01000001b ; E
.CODE
MOV AX,@DATA
MOV DS, AX
MAIN: MOV DX,2000h ; first DOT MATRIX digit
MOV CX, 5
MOV BX, offset Dots
NEXT MOV AL,[BX]
OUT DX,AL
INC BX
INC DX
LOOP NEXT
RET
16
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Handshaking
• Some I/O devices accept or release information
slower than the microprocessor.
• A method of I/O control called handshaking or
polling è synchronizes the I/O device with the
microprocessor.
• An example is a parallel printer that prints a few
hundred characters per second (CPS).
• The processor can send data much faster.
– a way to slow the microprocessor down to match
speeds with the printer must be developed
17
Figure 11–5 The DB25 connector found on computers and the Centronics 36-pin
connector found on printers for the Centronics parallel printer interface.
18
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• ASCII data are placed on D7–D0

• A pulse is then applied to the STB connection.
• BUSY indicates the printer is busy
• STB is a clock pulse used to send data to printer
• As the printer receives data, it places logic 1 on the
BUSY pin, indicating it is printing data
• The software polls the BUSY pin to decide whether
the printer is busy.
– If the printer is busy, the processor waits
– if not, the next ASCII character goes to the printer
• This process is called handshaking or polling.
19
BUSY is the I/O address of the input port receiving the BUSY signal from printer
BUSY = 1: printer is busy printing- do not send a new character
BUSY = 0: printer is not busy - send a new character now
;An assembly language procedure that prints the ASCII data byte in register BL.
PRINT PROC NEAR
.REPEAT ;Poll the busy line until it goes low
IN AL,BUSY ;READ the port having the BUSY input
TEST AL,BUSY_BIT_MASK ;test if the Busy bit in the data read is 0
Loop repeatedly reads ;BUSY_BIT is a mask defining the position
BUSY & checks if it is low
;of the BUSY bit in the port
.UNTIL ZERO ;End waiting loop if the ZERO flag is set
MOV AL,BL ;Yes!...move character data to AL
Here
BUSY = 0! OUT PRINTER,AL ;and output it to printer-
So output ;PRINTER is address of the printer port
data to
Printer!
;This also generates the #STB pulse
RET
PRINT ENDP
20
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Input Devices
• Input devices are already TTL and compatible
• Switch-based devices are either open or connected;
These are not TTL levels.
– TTL levels are a logic 0 (0.0 V–0.8 V)
– or a logic 1 (2.0 V–5.0 V)
Figure 11–6 A single-pole, single-throw switch interfaced as a TTL device.
21
• Mechanical switch contacts physically bounce when

they are closed,
– which can create a problem if a switch is used
as a clocking signal for a digital circuit
• To prevent problems with bounces, one of the
circuits shown in Fig 11–7 can be used.
– the first is a classic bounce eliminator
– second is a more practical version of the same
• The first version costs more to construct
– the second costs requires no pull-up resistors
and two inverters instead of two NAND gates
22
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Figure 11–7 Debouncing switch contacts: (a) conventional debouncing and (b)
practical debouncing.
– as the Q input from the switch becomes a logic 0,

it changes the state of the flip-flop
– if the contact bounces away from the Q input, the
flip-flop remembers, no change occurs, and thus
no bounce
23
Output Devices
• Output devices are more diverse than input devices,
but many are interfaced in a uniform manner.
• Voltages are TTL-compatible from the
microprocessor of the interfacing element.
– logic 0 = 0.0 V to 0.4 V
– logic 1 = 2.4 V to 5.0 V
• Currents for a processor and many interfacing
components are less than for standard TTL.
– Logic 0 = 0.0 to 2.0 mA
– logic 1 = 0.0 to 400 µA
24
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• The TTL inverter (standard version) provides up to

16 mA of current at a logic 0 level
– more than enough to drive a standard LED
Figure 11–8 Interfacing an LED: (a) using a transistor and

(b) using an inverter.
25
• TTL input signal has minimum value of 2.4 V

• Drop across emitter-base junction is 0.7 V.
• The difference is 1.7 V
• The value of the resistor is 1.7 V ÷ 0.1 mA or 17kW.
• In 11–8(a), we elected to use a switching transistor
in place of the TTL buffer.
26
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• Suppose we need to interface a 12 V DC 1A motor

to the microprocessor.
• We cannot use a TTL inverter:
– 12 V signal would burn out the inverter
– current far exceeds 16 mA inverter maximum
• We cannot use a 2N2222 transistor:
– maximum current is 250 mA to 500 mA,
depending on the package style chosen
• The solution is to use a Darlington-pair, such as a
TIP120.
27
Figure 11–9 A DC motor interfaced to a system by using a Darlington-pair.
– The Darlington-pair must use

a heat sink because of the
amount of current
– the diode must be present to
prevent the Darlington-pair
from being destroyed by
inductive kickback
28
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4/11/22
• Fig 11–9 illustrates a motor connected to the

Darlington-pair with a minimum current gain
of 7000 and a maximum current of 4A.
• Value of the bias resistor is calculated exactly the
same as the one used in the LED driver.
• The current through the resistor is 1.0 A ÷ 7000, or
about 0.143 mA.
• Voltage drop is 0.9 V because of the two diode
drops (base/emitter junctions).
• The value of the bias resistor is 0.9 V ÷ 0.143 mA
or 6.29K W.
29
Decoding 8-Bit I/O Port Addresses

• Fixed I/O instruction uses an 8-bit I/O port address
that on A15–A0 as 0000H–00FFH.
– we often decode only address connections
A7–A0 for an 8-bit I/O port address
• If the address is decoded as an 8-bit address, we
can never include I/O devices using a 16-bit address.
– the PC never uses or decodes an 8-bit address
30
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4/11/22
Figure 11–10 A port decoder that decodes 8-bit I/O ports. This decoder generates
active low outputs for ports F0H–F7H.
31
Figure 11–11 A PLD that generates part selection signals
32
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Decoding 16-Bit I/O Port Addresses

• PC systems typically use 16-bit I/O addresses.
– 16-bit addresses rare in embedded systems
• The difference between decoding an 8-bit and a 16-
bit I/O address is that eight additional address lines
(A15–A8) must be decoded.
• Figure 11–12 illustrates a circuit that contains a PLD
and a 4-input NAND gate used to decode I/O ports
EFF8H–EFFFH.
• PLD generates address strobes for I/O ports
33
Figure 11–12 A PLD that decodes 16-bit I/O ports EFF8H through EFFFH.
34
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4/11/22
16-bit Wide I/O: 8086,286, 386SX

• Same with memory banks, we have 64K Byte Ports
multiple I/O byte banks (each 1 byte)
• For processors with a 16-bit data bus:
2 banks (for low and high bytes)
• 64K 8-byte I/O ports à 32K 16-bit
ports (decoded using most significant
15 bits of the 16-bit I/O address)
32K Word Ports

• Which byte in the port is determined
by the LSB (A0) and the #BHE:
• For I/O writes, as with memory, use

separate strobe signals (e.g. #BLE or
#BHE) for the separate byte ports
• For reads, normally no action is
required as processor reads the byte MS byte port LS byte port
it wants. This is OK assuming the port
responds correctly to the read
command from the processor
35
Byte Selection in a 16-bit port
36
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16-bit Output Port which allows

µP the processor to write
Data Bus into either or both
its two separate bytes
A7 A1
40H = 0100 0000
I/O Write
Low Byte Port
This part
Is the same
For both byte ports
41H = 0100 0001

High Byte Port
D8
37
11–3 THE PROGRAMMABLE PERIPHERAL

• 82C55 programmable peripheral interface (PPI)
is a popular, low-cost interface component found in
many applications.
• The PPI has 24 pins for I/O, programmable in
groups of 12 pins and groups that operate in three
distinct modes of operation.
• 82C55 (CMOS version) can interface any TTL-
compatible I/O device to the microprocessor.
• The 82C55 requires wait states if operated with a
processor using higher than an 8 MHz clock.
• The 82C55 still finds application even in the latest Core2-
based computer system.
38
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many applications.
39

many applications.
40
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many applications.
41

many applications.
42
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• 82C55 is used for interface to the keyboard and

parallel printer port in many PCs.
– found as a function within an interfacing chip set
– also controls the timer and reads data from the
keyboard interface
• An experimentation board is available that plugs into
the parallel port of a PC, to allow access to an 8255
located on the board.
• The 8255 is programmed in either assembly
language or Visual C++ through drivers available
with the board.
43
Basic Description of the 82C55

• Fig 11–18 shows pin-outs of the 82C55 in
DIP and surface mount (flat pack) format.
• The three I/O ports (labeled A, B, and C) are
programmed as groups.
– group A connections consist of port A (PA7–PA0)
and the upper half of port C (PC7–PC4)
– group B consists of port B (PB7–PB0) and the
lower half of port C (PC3–PC0)
• 82C55 is selected by its CS pin for programming and
reading/writing to a port.
44
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Figure 11–18 The pin-out of the 82C55 peripheral interface adapter (PPI).
45
• Table 11–2 shows I/O port assignments used for

programming and access to the I/O ports.
• In the PC, a pair of 82C55s, or equivalents, are
decoded at I/O ports 60H–63H and also
at ports 378H–37BH.
• The 82C55 is a fairly simple device to interface to
the microprocessor and program.
• For 82C55 to be read or written, the CS input must
be logic 0 and the correct I/O address must be
applied to the A1 and A0 pins.
• Remaining port address pins are don’t cares.
46
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I/O Port Assignments
A1 A0 Function
• Group A is Port A and
upper ½ of Port C 0 0 Port A
(PC7-PC4). 0 1 Port B
• Group B is Port B and
lower ½ of Port C (PC3- 1 0 Port C
PC0).
1 1 Command Register
47
• Fig 11–19 shows an 82C55 connected to the

80386SX so it functions at 8-bit addresses C0H
(port A), C2H (port B), C4H (port C),
and C6H (command register).
– this interface uses the low bank of the I/O map
• All 82C55 pins are direct connections to the
80386SX, except the CS pin. The pin is
decoded/selected by a 74ALS138 decoder.
• A RESET to 82C55 sets up all ports as
simple input ports using mode 0 operation.
– initializes the device when the processor is reset
48
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Figure 11–19 The 82C55 interfaced to the low bank of the 80386SX microprocessor.
A1 A0 Inputs on 82C55
A7 A6 A5 A4 A3 A2 A1 A0
1 1 0 0 0 0 0 0 = C0H Port A
1 1 0 0 0 0 1 0 = C2H Port B
1 1 0 0 0 1 0 0 = C4H Port C
1 1 0 0 0 1 1 0 = C6H Comnd
Register
Select PPI
1 At decoded
0 001 µP address
0
1
0
0
Address from
80386SX
Dr. Imad Alzeer
microprocessor 0701441 ”Microprocessor Fundamentals” 49
49
• After a RESET, no other commands are needed, as

long as it is used as an input device for all three
ports.
• 82C55 is interfaced to the PC at port addresses
60H–63H for keyboard control.
– also for controlling the speaker, timer, and other
internal devices such as memory expansion
• It is also used for the parallel printer port at I/O ports
378H–37BH.
50
25

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4/11/22

Chapter 11: Basic I/O Interface

11–1 INTRO TO I/O INTERFACE

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 3

– in the PC, isolated I/O

Isolated vs. Memory Mapped

• A disadvantage of isolated I/O is that data transferred

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 8

The PC I/O space

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 9

03FF Must use 16-bit variable

Reserved for use by

Can Use either:

IN (I/O Read) & OUT (I/O Write)

OUT 23H,AL ;immediate

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 11

Basic Input Port (for I/O Reads)

• The basic input port connects an external set of bits

à Must include a 3-state (Tri-State) buffer to limit

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 12

The SEL signal is generated (active low) 3-state buffer

Basic Output Port (for I/O Writes)

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 14

Circuit can be expanded for

Data is latched and remains until the next OUT

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 15

5 x8 Dot Matrix Example

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 16

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 17

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 18

• ASCII data are placed on D7–D0

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 19

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 20

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 21

• Mechanical switch contacts physically bounce when

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 22

– as the Q input from the switch becomes a logic 0,

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 24

• The TTL inverter (standard version) provides up to

Figure 11–8 Interfacing an LED: (a) using a transistor and

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 25

• TTL input signal has minimum value of 2.4 V

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 26

• Suppose we need to interface a 12 V DC 1A motor

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 27

Figure 11–9 A DC motor interfaced to a system by using a Darlington-pair.

– The Darlington-pair must use

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 28

• Fig 11–9 illustrates a motor connected to the

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 29

Decoding 8-Bit I/O Port Addresses

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 30

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 31

Figure 11–11 A PLD that generates part selection signals

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 32

Decoding 16-Bit I/O Port Addresses

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 33

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 34

16-bit Wide I/O: 8086,286, 386SX

32K Word Ports

• For I/O writes, as with memory, use

Dr. Imad Alzeer 0701441 ”Microprocessor Fundamentals” 35