ECEg-M4161

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 I/O Interface

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 Issues

 Introduction

 I/O ports and devices

 Programmable peripheral Interfaces (PPI)

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 Introduction
I/O Problems
 Wide variety of peripherals
o Delivering different amounts of data
o At different speeds
o In different formats
 All slower than CPU and RAM
 Need I/O modules

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 Introduction
I/O Modules

 Interface to CPU and Memory

 Interface to one or more peripherals

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 Introduction
External Devices
 Human readable
Screen, printer, keyboard
 Machine readable
Monitoring and control
 Communication
Modem
Network Interface Card (NIC)

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 Introduction
I/O module functions

 Control & Timing

 CPU Communication
 Device Communication
 Data Buffering
 Error Detection

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 Introduction
I/O steps
 CPU checks I/O module device status
 I/O module returns status
 If ready, CPU requests data transfer
 I/O module gets data from device
 I/O module transfers data to CPU

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 Introduction
I/O Techniques

Programmed
Interrupt driven
Direct Memory Access (DMA)

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 I/O ports
Two types

1. Memory mapped I/O

2. Isolated I/O

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 I/O ports
Memory mapped I/O
 Uses instructions that transfers data between
microprocessor & memory
 Treated as memory location in the memory map
 Portion of memory is used as I/O map
 8086 uses M/IO control signal to select b/n
memory and I/O devices.

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 I/O ports
Isolated I/O
 I/O locations are isolated from memory system in a separate
address space.
 User can expand the memory to its full size
 Data transferred between I/O and microprocessor must be
access by IN/OUT instructions
 In PC, isolated I/O ports are used for controlling peripheral
device
 8-bit port address access devices located on system board.
16-bit port access serial, parallel ports, video & disk drive

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 I/O ports
I/O Addressing
Two addressing modes
1) Immediate port address
- Can only be 1 byte immediate address
- Can only address ports 00h through ffh
2) Port address present in DX
- Can address all ports 0000h through ffffh
- Can only use DX for port addresses
- Can only use AL,AX for port data

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 I/O ports
I/O Instructions
Two I/O instructions:
 Transfers information to an I/O device (OUT)
 Read information from an I/O device (IN)

When data are transferred using IN/OUT instruction, I/O

address (port number) appears on the address bus
 8-bit fixed port appears on address bus A7-A0
with A15-A8 bits equal to 00000000b
 16-bit variable port appears on address connection
A15-A0

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 I/O ports
I/O Instructions…e.g.

IN AL, p8 ;Read from port p8 to AL

IN AX, p8 ;Read from port p8 to AX
IN AL, DX ;Read from port addressed by DX to AL
IN AX, DX ;Read from port addressed by DX to AX
OUT p8 , AL ;Output from AL into port p8
OUT p8 , AX ;Output from AX into port p8
OUT DX, AL ;Output from AL into port addressed by DX

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 I/O Ports

I/O Port

Parallel I/O Serial I/O

A simple shift register can be used to change a serial Port

to parallel or vice versa

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 I/O Ports
Parallel I/O

Input
 Basic input device has a set of tri-state buffers.

 When microprocessors executes an IN instruction, I/O

port is decoded to generate logic 0 on SEL

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 I/O Ports… a simple I/P ckt.

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 I/O Ports
Parallel I/O

Output
 Basic output interface receives data from microprocessor
and must hold it.
Flip-flop latches (buffers) are built into these devices

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 I/O Ports…a simple O/P ckt.

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 PPI (Programmable peripheral interfaces)
Several developed by Intel to ease design burden
Provide a complete I/O interface on a single chip
Examples of common I/O interface chips:
8255A Programmable Peripheral Interface (PPI)
8259 Programmable Interrupt Controller (PIC)
8253/4 Programmable Interval Timer (PIT)
8237 Programmable DMA Controller
IBM PC/XT had these chips on system board
Modern PCs have functionality included in system chipset

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 PPI
8255 - Programmable Peripheral Interface
(Parallel Port Interface)
8 8
Data
Port A

RD 8
Port B
WR
4
RESET
CH

CS
A1
Port C
{ CL
4

A0

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 8086 Microprocessor
Interrupts

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 Interrupt

 The meaning of ‘interrupts’ is to break the sequence of operation.

 While the Microprocessor is executing a program, an ‘interrupt’ breaks the
normal sequence of execution of instructions, diverts its execution to some
other program called Interrupt Service Routine (ISR).
After executing , control returns the back again to the main
program.

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 Types of interrupts
 Hardware Interrupts

 Maskable & Non-Maskable Interrupts

 Software Interrupts

 256 Interrupts

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 The processor can be interrupted in the following ways

i) by an external signal generated by a peripheral,

ii) by an internal signal generated by a special instruction in the program,
iii)by an internal signal generated due to an exceptional condition which
occurs while executing an instruction.

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 Interrupts

Software Interrupt
Hardware Interrupts
(INT n)

Non-Maskable 256 Types Of

Maskable Interrupts
Interrupts Software
Interrupts

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 Hardware Interrupts

The interrupts initiated by external hardware

by sending an appropriate signal to the
interrupt pin of the processor is called
hardware interrupt. The 8086 processor has two
interrupt pins INTR and NMI. The interrupts
initiated by applying appropriate signal to these
pins are called hardware interrupts of 8086.

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 Interrupts

Hardware
Interrupt
s

Maskable Non-Maskable
Interrupts Interrupts

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 Interrupts

Hardware
Interrupt
s

Maskable Non-Maskable
Interrupts Interrupts

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 Interrupts

Hardware
Interrupts

Maskable Non-Maskable
Interrupts Interrupts

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 Hardware Interrupts

Used to handle external hardware

peripherals , such as key boards , mouse
, hard disks , floppy disks , DVD drivers,
and printers.

key boards mouse hard disks floppy disks DVD drivers

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Maskable & Non-Maskable Interrupts

The processor has the facility for accepting or rejecting

hardware interrupts. Programming the processor to reject an
interrupt is referred to as masking or disabling and programming
the processor to accept an interrupt is referred to as unmasking
or enabling. In 8086 the interrupt flag (IF) can be set to one to
unmask or enable all hardware interrupts and IF is cleared to
zero to mask or disable a hardware interrupts except NMI. The
interrupts whose request can be either accepted or rejected by the
processor are called maskable interrupts.

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 The interrupts whose request has to be definitely accepted (or cannot be
rejected) by the processor are called non-maskable interrupts. Whenever a
request is made by non-maskable interrupt, the processor has to definitely
accept that request and service that interrupt by suspending its current
program and executing an ISR. In 8086 processor all the hardware
interrupts initiated through INTR pin are maskable by clearing interrupt
flag (IF). The interrupt initiated through NMI pin and all software
interrupts are non-maskable.

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 Maskable & Non-Maskable Interrupts

The programmer
Interrupts cannot control when a
Non-Maskable
Interrupts
Hardware is serviced
Interrupts
The processor has to
stop the main
Maskable Non-Maskable program to execute
Interrupts Interrupts the NMI service
routine

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 Maskable & Non-Maskable Interrupts

Interrupts

Hardware The programmer can

Interrupt choose to mask
s specific interrupts and
re-enable them later.
Maskable Non-Maskable
Interrupts Interrupts

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 Non-Maskable Interrupts

Used during power failure

Used during critical response time

Used during non-recoverable hardware errors

Used during memory parity errors

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 Software Interrupts

The software interrupts are program

instructions. These instructions are inserted
at desired locations in a program. While
running a program, if software interrupt
instruction is encountered then the processor
initiates an interrupt. The 8086 processor has
256 types of software interrupts. The software
interrupt instruction is INT n, where n is the
type number in the range 0 to 255.

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 Software Interrupt (INT n)

Used by operating systems to provide

hooks into various function

Used as a communication mechanism

between different parts of the program

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 8086 INTERRUPTTYPES
256 INTERRUPTS OF 8086 ARE DIVIDED IN TO 3 GROUPS

1. TYPE 0 TOTYPE 4 INTERRUPTS-

These Are Used For Fixed Operations And Hence Are
Called Dedicated Interrupts

2. TYPE 5 TOTYPE 31 INTERRUPTS

Not Used By 8086, reserved For Higher Processors
Like 80286
80386 Etc

3. TYPE 32 TO 255 INTERRUPTS

Available For User, called User Defined Interrupts These
Can Be H/W Interrupts And Activated Through Intr Line Or
Can Be S/W Interrupts.

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IVT:- 003FF
H
Type FFH Interrupt (Available)

003FC
Available Interrupts
H
(224)
Type 21H Interrupt (Available)
00084H
Type 20H Interrupt (Available)
00080H
Type 1FH Interrupt
0007C
H
(Reserved) Reserved Interrupts
(27)
1 KB

Type 05H Interrupt (Reserved)

00014H
Type 04H Interrupt (Over Flow)
00010H
Type 03H Interrupt (Break Point)
0000C
H Type 02H Interrupt (NMI)
00008H Type 01H Interrupt Dedicated Interrupts
0004F (Trap or Single
H step) (05)

CS 0003FH Type 00H Interrupt

00002H (Divide by Zero)
IP
00001H 41
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 8259A PROGRAMMABLE INTERRUPT
CONTROLLER

8259A (PIC) adds eight vectored priority encoded interrupts to the

microprocessor.

Expandable, without additional hardware, to accept up to 64 interrupt

requests.

It requires a master 8259A & eight 8259A slaves.

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 General Description of the 8259A

8259A is easy to connect

to the microprocessor used to request
because all of its pins are an interrupt and
to connect to a
direct connections except slave in a
the CS pin, which must system with
be decoded, and the WR multiple 8259As.

pin, which must have an

I/O bank write pulse.

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 8259A Pin-Outs

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 CAS0–CAS2
Thecascade lines are used as outputs from the master to the slaves for
cascading multiple 8259As in a system.

SP/EN
Slave program/enable buffer is a dual-function pin.

when the 8259A is in buffered mode, this output controls the data bus
transceivers in a large microprocessor-based system.

when the 8259A is not in the buffered mode, this pin programs the device as
a master (1) or a slave (0).

Remember that we can connect PIC's together. This allows us to provide

support for up to 64 IR numbers. In other words--64 hardware interrupts.
CAS0, CAS1, and CAS2 pins provide a way to send signals between these
PIC's.

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 46 46
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 Connecting a Single 8259A
Fig. 12–16 shows a single 8259A connected to the microprocessor.
Here the pin SP/EN* is pulled high to indicate that it is a master.

The 8259A requires four wait states for it to function properly with a
16 MHz 80386SX more for some other versions of the Intel
microprocessor family.

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 SP=1 (Master)

PIC is slow, so it
needs torequest
wait states,
particularly with
recent faster
processors

I/O port (PLD)

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 49 49
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 Direct Memory Access (DMA)

50
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 DMA
• Direct Memory Access (DMA) is a method whereby
the memory and I/O space of the microprocessor
can be accessed directly without the intervention of
the microprocessor or a program.
• To request DMA access, the DMAC raises the HOLD
input high.
• The microprocessor responds by floating the 3
buses and raising HLDA high to indicate that a hold
is in effect.
• The DMAC can now use the 3 buses to do DMA
transfers on them- bypassing the processor

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• During a HOLD, the microprocessor stops
running the program and places its address,
data, and control bus connections at their
High state. This in effect is the same as
removing the microprocessor from its socket!
• While the microprocessor is held, other
devices are free to gain access to its memory
and I/O space and transfer data directly using
them
• Usually this requires the use of a
programmable DMAC chip: (Direct Memory
Access Controller), e.g. the 8237A

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• HOLD is sampled during instruction execution while
interrupt signals are sampled at the end of instructions
• HOLD takes effect (HLDA generated) in a clock cycle
or two
 So, Hold has a higher priority than interrupts
• The only input with a higher priority than HOLD is the
RESET input to the microprocessor.

DMA finished

Device Requests
I/P DMA Transfer

DMA Request
O/P Granted- mP has relinquished
control of the buses

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 DMA Applications
• Wherever large amounts of data need to be
transferred fast between memory and an I/O
peripheral device, e.g.
- Hard disk, CD
- Video memory to refresh display
- Sound cards
- Network cards
- Data acquisition boards
• Also for row address generation by hardware to
refresh large DRAMs fast

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 I/O
Write
Memory
HOLD Read
C

Simultaneously !
Memory address
Generated by fast
Counters on the DMAC

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 DMA Control Signals
• Because during a DMA both memory and an I/O
device may be accessed simultaneously, the DMAC
may need to generate:
- #MRDC and #IOWC (simultaneously) for memory
to I/O device transfers
- #IORC and #MRWC (simultaneously) for I/O device
to memory transfers

This was not necessary with programmed I/O as

processor either accessed memory or an I/O device
at any given time moving data between it and the
processor

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 DMAC Interface

With HLDA
Active

Two types of DMA data transfers: The DMAC is a

Programmable I/O device
1. Sequential DMA: for the microprocessor,
Just like the PPI, PIC,
Read then Write through the DMAC UART, …
Data rests in DMAC. Only M or IO DMA activities by the DMAC
controls are needed at any given time will be programmed into it by
the processor before hand
2. Simultaneous DMA:
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Data moved directly between peripheral and memory. Both M & IO controls used at the same time 57
 The 8237A Programmable DMAC
• Four separate prioritized DMA channels
(expandable by using multiple DMACs)
• Transfer rates up to 1.6 M bytes/s Address bus
(during DMA)
• DMA transfers by the DMA channels are
programmed a priori into the DMAC by
the processor On-chip
Address I/Ps

• Can address 64KB of memory in one mP  16 I/O adrs

(Programming)

programming operation
 16-bit addresses - Data Bus
(during
For address
• Allows the following DMA transfer Counters Programng)
- A8-A15
During DMA
combinations: DMA
- Memory to peripheral Device
- Peripheral to memory
- Peripheral to peripheral
- Memory to memory
• No longer used on the PC in chip form nowadays- its
functionality has been embedded into modern chip set ICs

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 Programming the DMAC

(Only these 3 numbers are written into the DMAC)

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 DMA Modes: Byte, Burst & Block (3 Bees!)
Bars show
duration
of DMAC
controlling
the buses

Only
for
a
byte

(buffer full)
As long (buffer full)
As Device
Is Ready Block finished?
(filling its buffer)
As long
as needed
to transfer the block
DMAC gets more greedy for bus control

Byte: Burst: (a buffer-full of data) Block: (multiple buffers)

Un-buffered device Fill the buffer of a slow device once Fill the buffer of a fast
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 Comparison between the three types of I/O
Type Advantages Disadvantages
- Fastest response to device request - Wasted processor
Polling - Simplest hardware and software resources
(always waiting)
- More efficient use of processor time - Delay in response time to
Interrupt- (Processor executes program- interrupt (interrupt latency)
based checks for interrupts only at the end - Overhead due to interrupt
of every instructions) processing, e.g. saving
return address & registers,
context switching
- Increased cost and
complexity of hardware
and software
- Fastest data transfer rates - Need a DMAC device
DMA (approaching those determined by - Highest cost and
memory/device access time) complexity in hardware
Address generation by fast DMAC and software
hardware- not by processor software

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