UNIT

03

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Input/Output (I/O) Organisation

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Names of Sub-Units
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Introduction to Input/Output (I/O) Organisation, Accessing I/O Devices, Interrupts: Interrupt
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Hardware, Direct Memory Access, Buses, Standard I/O Interfaces: PCI Bus, SCSI Bus, Universal Serial
Bus (USB).
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Overview
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This unit begins by learning about accessing the input/output devices. Then, the unit discusses the
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interrupt hardware and direct memory access. Next, the unit explain the buses. Towards the end, the
unit discusses the standard i/o interfaces.
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Learning Objectives
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In this unit, you will learn to:

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aa Explain the significance of accessing the I/O devices

aa Describe the concept of hardware interrupt
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aa Define the use of direct memory access

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aa Explain the concept of buses

aa Describe the standard input/output interfaces
JGI JAIN
DEEMED-TO-BE UNIVERSITY
Computer Organization and Architecture

Learning Outcomes

At the end of this unit, you would:

aa Analyse the use of accessing the I/O devices
aa Assess the knowledge about the hardware interrupt
aa Explore the use of direct memory access
aa Evaluate the concept of buses

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aa Assess the knowledge about the standard input/output interfaces

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Pre-Unit Preparatory Material

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aa http://www.cse.iitm.ac.in/~vplab/courses/comp_org/Input_Output_Organization_11.pdf

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3.1 Introduction

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An efficient means of communication between the central system and the outside world is provided by
a computer’s I/O subsystem. It is in charge of the computer system’s input/output processes.
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Peripheral devices are input or output devices that are connected to a computer. These devices, which
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are regarded to be part of a computer system, are designed to read information into or out of the
memory unit in response to commands from the CPU.
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3.2  Accessing I/O Devices

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A single bus configuration is a straightforward way to connect I/O devices to a computer. The bus allows
all of the devices connected to it to communicate with one another. It usually has three sets of lines for
IG

carrying address, data, and control signals. A unique set of addresses is assigned to each I/O device.
The device that recognises a certain address responds to the commands sent on the control lines when
the processor places that address on the address line. When I/O devices and memory share the same
address space, the CPU requests either a read or a write operation, and the required data is sent via the
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data lines, the arrangement is known as memory-mapped.

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Any machine instruction that can access memory can be used to transport data to or from an I/O device
when memory-mapped I/O is employed. If DATAIN is the address of the keyboard’s input buffer, the
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instruction will be executed. For example,

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Move DATAIN, R0
The data from DATAIN is read and stored in processor register R0. Likewise, the instruction:
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Move R0, DATAOUT

Sends the contents of register R0 to location DATAOUT, which might be a display unit’s or printer’s
output data buffer.
Memory-mapped I/O is used in the majority of computer systems. To execute I/O transfers, certain CPUs
feature specific In and Out instructions. When designing a computer system based on these CPUs, the
designer might link I/O devices to utilise the dedicated I/O address space or simply include them in the

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memory address space. The low-order bits of the address bus are examined by the I/O devices to decide
if they should reply. To connect an I/O device to the bus, you’ll need the following hardware. When the
device’s address appears on the address lines, the address decoder allows it to recognise it. The data
register stores the information being sent to or received by the processor. The status register includes
information about the I/O device’s functioning. The data and status registers are both connected to the
data bus and have their own addresses. The device’s interface circuit consists of the address decoder,
data and status registers, and the control circuitry necessary to coordinate I/O transfers.
I/O devices run at rates that are significantly slower than the processor. When a human operator
types characters on a keyboard, the CPU may process millions of instructions in the time between each

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character entry. Only when a character is available in the keyboard interface’s input buffer should an
instruction to read a character from the keyboard be performed. We must also ensure that each input

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character is only read once. Figure 1 shows accessing the I/O devices:

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Memory-Mapped I/O (1)
Memory Address Space

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Two Address One Address Space Two Address Space

OxFFFF... Memory

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I/O ports

S
0 (a) (b) (c)
E I/O Address Space
(a) Separate I/O and Memory space
R
(b) Memory-mapped I/O
(c) Hybrid
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Figure 1: Accessing I/O Device

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3.3 Interrupts
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When a process or event requires immediate attention, hardware or software emits an interrupt
signal. It notifies the processor of a high-priority task that requires the present working process to be
interrupted. One of the bus control lines in I/O devices is devoted to this function and is known as the
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Interrupt Service Routine (ISR).

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3.3.1  Interrupt Hardware

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We said that an I/O device requests an interrupt by activating the interrupt-request bus line. Almost all
computers have several I/O devices that can request an interrupt. As shown, a single interrupt-request
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line can be utilised to service n devices. Switches to ground are used to connect all devices to the line. A
device shuts its connected switch to request an interrupt. The voltage on the interrupt-request line will
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be equal to Vdd if all interrupt-request signals INTR1 to INTRn are inactive, that is, if all switches are
open. This is the line’s dormant state. Because the line voltage will drop to zero if one or more switches
are closed, the value of INTR is the logical OR of the requests from individual devices, that is, INTR
INTR = INTR1 + ………+INTRn
The complemented form is commonly used. INTR, to refer to the interrupt-request signal on the common
line, which is active while the voltage is low.

 3
JGI JAIN
DEEMED-TO-BE UNIVERSITY
Computer Organization and Architecture

3.4 Direct Memory Access

A brief overview of how the CPU may transmit data to or from a number of external (non-memory)
devices was given during the discussion on computer architecture and the role of the Central Processing
Unit. The operation used address, data lines, and WR RD control lines to read and write to the I/O system
in the same way it did memory.
This necessitates CPU involvement and is time-consuming. Direct Memory Access (DMA) refers to an
I/O subsystem’s ability to transmit data to and from a memory subsystem without the need for a CPU.
A DMA controller is a device that controls data transfers between an I/O subsystem and a memory

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subsystem in the same way that a CPU does. The following are the elements of DMA:
DMA controller: The DMA controller can send orders to the memory that are identical to the CPU’s

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zz
directives. In a way, the DMA controller is a second CPU in the system, although it is dedicated to
I/O. The DMA controller, links one or more I/O ports directly to memory, with the I/O data stream

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passing via the DMA controller faster and more effectively than through the CPU since the DMA
channel is dedicated to data transport.

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Figure 2 shows the DMA controller:

E
S
Address bus

Data bus
Data bus
buffers
E Address bus
buffers
R
Address register
Internal bus
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DMA select DS
Register select RS
H

Word count register

Read RD
Control
Write WR
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logic
Bus request BR Control register
Bus grant BG
DMA request
Interupt Interupt
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DMA Acknowledge to I/O device

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Figure 2: DMA Controller

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zz The DMA interface: Because a DMA controller has independent memory access, it adds another
layer of complexity to the I/O interface. A single transaction can be carried on a single pair of wires
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(bus). If a DMA and a microprocessor share a signal wire to memory, a method must be in place to
determine who gets access to memory when both try at the same time.
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zz DMA interface operation: A typical direct memory-access controller interface. In this DMA-
controlled example, the I/O ports are solely connected to the DMA controller. Signal lines are the
identical ones that connect the ports to the processor in most cases. Memory lines are similar to
regular lines, except that they are used by both the CPU and the DMA controller. The HALT and
HALT ACKNOWLEDGE lines are the two new lines. The DMA controller and the CPU are synchronised
using these lines. When the DMA controller wants to access memory, it asserts the HALT signal,
which causes the CPU to halt.

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At a later time, the CPU reacts with HALT ACKNOWLEDGE, and the DMA controller takes control of
memory. The DMA controller removes its HALT request after it completes its work, the processor
resumes its suspension, and the HALT ACKNOWLEDGE is removed. A third form of DMA request
is the dotted IMMEDIATE HALT. Due to the time it takes for the CPU to reach a condition where it
may halt operations, the processor may take several clock cycles to recognise the HALT request.
Data kept in dynamic registers that are updated during regular processing must be transferred to
status registers, otherwise the data is no longer required. The IMMEDIATE HALT line eliminates the
wait, but it comes with a slew of limitations. The IMMEDIATE HALT can only be used once or twice,
otherwise the processor may not be able to appropriately recover its state and resume the halted

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operation. Figure 3 shows the DMA controller interface:

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Interrupt

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Random-access
BG memory (RAM)
CPU

R
BR
RD WR Addr Data RD WR Addr Data

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Read Control
Write Control

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Data Bus
E Address Bus
R
Address
select

RD WR Addr Data
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DMA Aok.
DS
H

RS I/O
DMA
Controller Peripheral
BR
device
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BG DMA Request

Interrupt
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Figure 3: DMA Controller Interface

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3.5 Buses
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The Central Processing Unit (CPU), memory chips, and input/output (I/O) devices are all components
of a conventional computer system. A bus is a cable or a common channel that connects these diverse
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subsystems. As a result, the bus allows the various components to interact with one another.
In computer terms, a bus is a conduit that allows data to move between units or devices. It usually
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has access points, which are locations where a device may tap to join the channel. The majority of
buses are bidirectional, meaning that devices may transmit and receive data. A bus is a form of public
transportation that connects people from various locations’ devices.
It permits the addition of new peripheral devices and the mobility of peripheral devices across various
computer systems. When too many devices are linked to the same bus, however, the bus’ bandwidth
might constitute a bottleneck. A bus usually contains more than two devices or subsystems, and channels
linking only two components are sometimes referred to as ports rather than buses.

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JGI JAIN
DEEMED-TO-BE UNIVERSITY
Computer Organization and Architecture

Figure 4 shows the bus:

Proc Men

Device 1 Device 2

Figure 4: Bus

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Some important concepts related to buses are as follows:
zz Bus protocols: Because a bus is a communication channel used by numerous devices, rules must

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be created to ensure that communication occurs appropriately. The regulations are referred to as
bus protocols. The width of the data bus, data transfer size, bus protocols, timing, and other factors

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all play a role in bus architectural design. Buses are classed as synchronous or asynchronous
depending on whether or not the transactions are regulated by a clock. Parallel and serial buses are

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distinguished by whether data bits are transmitted on parallel cables or multiplexed onto a single
wire.

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zz Synchronous and asynchronous buses: Bus activities are synchronised with reference to a clock

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signal in a synchronous bus. Although the bus clock is usually taken from the computer system
clock, it is frequently slower than the master clock. 66MHz buses, for example, are utilised in systems
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with CPU speeds exceeding 500MHz. Because memory access periods are generally longer than
processor clock cycles, buses have traditionally been slower than processors. Although many people
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refer to the cycles as a bus cycle, a bus transaction might take many clock cycles.
Figure 5 shows the for a synchronous read operation:
T
H

T1 T2 T3
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Clock

Status
Status signals
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lines

Address
Stable address
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lines

Address
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enable

Data
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Valid data in
lines
Resd
cycle
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Resd

Data
Valid data out
Write lines
Cycle

Write

Figure 5: Synchronous Read Operation

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There is no system clock on an asynchronous bus. Handshaking is used to ensure that data is sent correctly
between the transmitter and the receiver. The bus master places the address and control signals on the
bus before asserting a synchronisation signal in an asynchronous read operation. The slave is prompted
to become synchronised by the master’s synchronisation signal, and after it has accessed the data, it
asserts its own synchronisation signal. The synchronisation signal from the slave informs the processor
that there is valid data on the bus, which it reads. After then, the master deasserts its synchronisation
signal, signalling to the slave that the master has read the data. The slave’s synchronisation signal is
then deasserted. A complete handshake is the name for this type of synchronisation. It’s worth noting
that there’s no clock and that the beginning and conclusion of the data transfer are signalled by specific

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synchronisation signals. A pair of Finite State Machines (FSMs) that function in such a way that one FSM
does not advance until the other FSM has achieved a specific state might be called an asynchronous

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communication protocol. Figure 6 shows the for an asynchronous read operation:

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t1 t2 t3

R
addr Address Valid
data Data Valid

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RD
MA

S
MSYN
SSYN
Time
E
R
Figure 6: Asynchronous Read Operation
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3.6  Standard I/O Interfaces

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The processor bus is the bus that is used by the processor chip’s signals. This bus can be used to link
devices that require very high-speed connectivity to the processor, such as the main memory. Only a
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few gadgets can be linked in this way due to electrical issues. A second bus is generally provided by the
motherboard, which can handle extra devices.
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The two buses are linked by a circuit, which we’ll refer to as a bridge, that converts one bus’s signals
and protocols into those of the other. The CPU sees devices attached to the extension bus as if they were
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connected directly to the processor’s own bus. Only the bridge circuit adds a tiny delay to data flows
between the CPU and those devices.
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It is impossible to create a universal processor bus standard. The architecture of the CPU is intimately
linked to the topology of this bus. It is also influenced by the processor chip’s electrical properties, such
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as its clock speed. Because the extension bus is not constrained by these constraints, it may employ
a standardised signalling method. A variety of guidelines have been created. Some have emerged by
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accident, as a result of a commercially successful design. For example, IBM created the ISA (Industry
Standard Architecture) bus for its PC AT (Personal Computer at the Time).
Some standards have been created by collaborative efforts among industries, even among competitors,
motivated by a common desire to have interoperable goods. Organisations like the IEEE (Institute of
Electrical and Electronics Engineers), ANSI (American National Standards Institute), and international
organisations like the ISO (International Standards Organisation) have granted these standards formal
status in some circumstances.

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JGI JAIN
DEEMED-TO-BE UNIVERSITY
Computer Organization and Architecture

3.6.1  Peripheral Component Interconnect (PCI) Bus

The PCI bus is an excellent example of a system bus that arose from a desire for standardisation. It
provides functionalities located on a processor bus bit in a defined format that is not specific to any
processor. The CPU sees devices linked to the PCI bus as if they were connected directly to the processor
bus. They are given addresses in the processor’s memory address area.
The PCI is based on a series of bus specifications that were largely utilised in IBM PCs. The 8-bit XT bus was
used in early PCs, and its signals were quite similar to Intel’s. Processors with the 80x86 instruction set.
The ISA bus was later named after the 16-bit bus used in PC At computers. The EISA bus is the expanded

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32-bit version of the bus. The Microchannel, which is used in IBM PCs, and the NuBus, which is used in
Macintosh computers, are two more buses developed in the 1980s with comparable characteristics.

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The PCI bus was created as a low-cost, processor-independent bus. Its design anticipated a rapidly rising

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requirement for bus capacity to accommodate high-speed discs, graphic and video devices, as well as
multiprocessor systems’ specific demands. As a result, over a decade after its introduction in 1992, the

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PCI is still widely used as an industry standard. A plug-and-play capability for connecting I/O devices is
an essential feature that the PCI pioneered. The user simply attaches the device interface board to the

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bus to connect a new device. The remainder is handled by the programme.

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Data Transfer
E
Most memory transfers in today’s computers use a burst of data rather than a single word. The reason
for this is that contemporary CPUs have cache memory built in. Data is transmitted in bursts of multiple
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words between the cache and the main memory. The words involved in such a transfer are stored in
different memory regions at different times. When the processor (in this case, the cache controller)
requests a read operation from the main memory, the memory replies by delivering a series of data
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words beginning at that address. Similarly, during a write operation, the processor provides a memory
address followed by a series of data words, which are written in order starting at the address. The PCI
H

was created with this manner of operation in mind. A single-word read or write operation is simply
considered as a burst of length one.
IG

Device Configuration
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When a computer is linked to an I/O device, many steps must be taken to setup both the hardware and
the software that interfaces with it.
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The PCI streamlines this procedure by including a tiny configuration ROM memory in each I/O device
interface that saves information about that device. In the configuration address space, all devices’
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configuration ROMs are accessible. When the system is powered up or reset, the PCI initialisation
software reads these ROMs. It detects if the device in question is a printer, a keyboard, an Ethernet
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interface, or a disc controller in each scenario. It can also learn about different device features and
choices.
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During the startup procedure, addresses are allocated to devices. This implies that devices that have
not yet been allocated an address cannot be accessible during the bus setup procedure. As a result,
the configuration address space employs a unique technique. IDSEL#, or Initialisation Device Select, is
an input signal that each device possesses. In the PC world, the PCI bus has acquired a lot of traction.
Many other systems, such as SUNs, employ it to take advantage of the large range of I/O devices that a
PCI interface may support. The PCI-processor bridge circuit is built on the processor chip itself in some
processors, such as the Compaq Alpha, simplifying system design and packaging even more.

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DEEMED-TO-BE UNIVERSITY

3.6.2  SCSI Bus

Small Computer System Interface is abbreviated as SCSI. It refers to the ANSI-defined X3.131 standard
bus. Devices like discs are linked to a computer via a 50-wire connection that may be up to 25 metres long
and transport data at up to 5 megabytes per second, according to the standard’s initial requirements.
The SCSI bus standard has gone through several modifications, and its data transmission capability
has almost doubled every two years. SCSI-2 and SCSI-3 have been specified, with several choices for
each. When a SCSI bus has eight data lines, it is referred to as a narrow bus, and data is sent one byte
at a time. A wide SCSI bus, on the other hand, contains 16 data lines and transmits data in 16 bits at a
time. There are also a variety of electrical signalling schemes to choose from. In the same manner that

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devices attached to the processor bus are not part of the CPU’s address space, devices linked to the
SCSI bus are not. Through a SCSI controller, the SCSI bus is linked to the processor bus. DMA is used by

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this controller to transport data packets from main memory to the device and vice versa. A packet can
include a data block, orders from the CPU to the device, or device status information.

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Consider how the SCSI bus may be utilised with a disc drive to demonstrate how it works. The connection

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with a disc drive is very different from the contact with the main memory. An initiator or a target are
the two types of controllers linked to a SCSI bus. An initiator can choose a specific target and transmit

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orders defining the actions to be carried out. Clearly, the processor’s controller, such as the SCSI
controller, must be capable of acting as an initiator. As a target, the disc controller is used. It executes

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the orders given to it by the initiator. The initiator creates a logical link with the intended recipient. Once
established, this connection can be interrupted and resumed as needed to send instructions and data
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bursts. Other devices can utilise the bus to transport data when a particular connection is suspended.
One of the major aspects of the SCSI bus that contributes to its great performance is its ability to overlap
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data transfer requests.
The target controller is always in charge of data transfers on the SCSI bus. To transmit a command
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to a target, an initiator first requests control of the bus, then picks the controller it wishes to interact
with and gives control of the bus onto it after winning arbitration. The controller then initiates a data
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transmission operation in order to receive the initiator’s command. The CPU issues an instruction to the
SCSI controller, which sets in motion the following series of events:
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1. The SCSI controller competes for control of the bus as an initiator.

2. If the initiator wins the arbitration, it chooses the target controller and gives it control of the bus.
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3. The initiator sends a command indicating the needed read operation in response to the target
starting an output operation (from initiator to target).
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4. The destination, recognising that it must first execute a disc search operation, sends a message to
the initiator indicating that the connection between them will be momentarily suspended. The bus
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is then released.
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5. The target controller instructs the disc drive to advance the read head to the first sector in the
desired read operation. The data contained in that sector is then read and stored in a data buffer.
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The target requests control of the bus when it is ready to begin transmitting data to the initiator.
6. The target sends the contents of the data buffer to the initiator before disconnecting the connection.
Depending on the bus width, data is transmitted in 8 or 16 bits in parallel.
7. The disc drive receives a directive from the target controller to execute another seek operation.
The contents of the second disc sector are then sent to the initiator as previously. The logical link
between the two controllers is severed at the end of these transfers.

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JGI JAIN
DEEMED-TO-BE UNIVERSITY
Computer Organization and Architecture

8. After receiving the data, the initiator controller uses the DMA method to put it in the main memory.
9. The CPU receives an interrupt from the SCSI controller indicating that the desired operation has
been performed.

The messages exchanged over the SCSI bus are at a higher level than those transferred via the CPU bus,
as seen in this instance. A “higher level” message in this sense refers to actions that, depending on the
device, may need many stages to accomplish. The CPU and the SCSI controller do not need to be aware
of the specifics of the device involved in a data transfer. The processor is not required to participate in
the disc search procedure in the preceding case.

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3.6.3  Universal Serial Bus (USB)

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Computer-communications synergy is at the heart of today’s information technology revolution.

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Keyboards, microphones, cameras, speakers, and display devices are likely to be used in a modern
computer system. A wired or wireless Internet connection is available on most PCs. A crucial necessity in

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such an environment is the availability of a simple, low-cost method to link these devices to the computer,
and the advent of the Universal Serial Bus represents a significant recent advance in this respect (USB).

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Low-speed (1.5 megabits/s) and full-speed (12 megabits/s) operation are supported by the USB. The most
recent edition of the bus standard (USB 2.0) added a third operating speed, known as high-speed (480

S
megabits/s). The USB is rapidly gaining commercial popularity, and with the inclusion of high-speed
capabilities, it may easily become the preferred connecting mechanism for most computer equipment.
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The USB has been designed to meet several key objectives:
R
zz Provides a simple, low-cost, and simple-to-use connectivity solution that solves the challenges posed
by a computer’s restricted number of I/O ports.
Support a variety of data transmission characteristics for I/O devices, such as phone and Internet
T

zz
connections.
H

zz Increase user convenience by enabling “plug-and-play” operation.

IG

Port Limitation
The parallel and serial ports mentioned in the preceding section provide a general-purpose point of
R

connection for connecting a computer to a variety of low-to medium-speed devices. A normal computer
only has a couple of these ports for practical reasons.
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Characteristics of the Device

P

The gadgets that can be linked to a computer can perform a wide range of tasks. Data transmissions to
and from such devices are subject to a wide range of speed, volume, and timing restrictions.
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A wide range of basic devices that may be connected to a computer produce data that is similar in
C

nature - slow and asynchronous. Computer mice, as well as video game controllers and manipulators,
are ideal examples.

Plug-and-Play
As computers grow more integrated into daily life, their existence should become more apparent. When
running a home theatre system with at least one computer, for example, the user should not be required
to switch the computer off or restart the system in order to connect or disconnect a device.

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A new device, such as an additional speaker, may be attached at any moment while the system is
running, thanks to the plug-and-play function. The system should immediately detect the presence of
this new device, identify the relevant device-driver software and any other facilities required to serve
it, and create the necessary addresses and logical connections to allow them to interact. The necessity
for plug-and-play has ramifications at all levels of the system, from hardware to operating system
and application software. One of the major goals of the USB design was to allow for plug-and-play
functionality.

USB Architecture

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The necessity for an interconnection system that combines low cost, flexibility, and high data-transfer
capacity has been highlighted in the preceding debate. I/O devices may also be physically separated

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from the computer to which they are attached. When large bandwidth is required, a broad bus carrying
8, 16, or more bits in parallel is typically used. A high number of wires, on the other hand, adds expense

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and complexity while also being troublesome for the user.

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Because of the data skew problem, it’s also difficult to build a broad bus that can transport data over a
long distance. With increasing distance, the number of skew rises, limiting the quantity of data that can

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be utilised.

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For the USB, a serial communication protocol was chosen because it meets the low-cost and flexibility
criteria. The clock and data information are combined and sent as a single signal. As a result, data skew
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imposes no restrictions on clock frequency or distance. As a result, a high clock frequency may be used
to provide a large data transmission bandwidth. As previously stated, the USB provides three-bit rates
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ranging from 1.5 to 480 megabits/s to accommodate the demands of various I/O devices.
The USB has the tree structure to support a large number of devices that may be added or deleted at
T

any moment, is shown in Figure 7:

H
IG

Host Computer

Root Hub
R

Hub Hub
Y
P

Hub I/O devices I/O devices I/O devices

O

I/O devices I/O devices

C

Figure 7: USB Tree Structure

A hub is a device that functions as an intermediary control point between the host and the I/O devices
at each node of the tree. A root hub at the bottom of the tree links the entire tree to the host computer.
The I/O devices being served (for example, a keyboard, an Internet connection, a speaker, or a digital
television) are represented by the tree’s leaves, which are referred to as functions in USB language. We’ll
refer to these devices as I/O devices to keep things consistent with the rest of the book.

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JGI JAIN DEEMED-TO-BE UNIVERSITY
Computer Organization and Architecture

Conclusion 3.7 Conclusion

zz Input/output architecture is a method of regulating interaction with the outside world through a
system of input/output architecture.
zz Peripheral devices are input or output devices that are connected to a computer.
zz A single bus configuration is a straightforward way to connect I/O devices to a computer.
zz A unique set of addresses is assigned to each I/O device. The device that recognises a certain address

D
responds to the commands sent on the control lines when the processor places that address on the
address line.

E
zz Memory-mapped I/O is used in the majority of computer systems. To execute I/O transfers, certain
CPUs feature specific In and Out instructions.

V
zz When a process or event requires immediate attention, hardware or software emits an interrupt
signal. It notifies the processor to a high-priority task that requires the present working process to

R
be interrupted.

E
zz Direct Memory Access (DMA) refers to an I/O subsystem’s ability to transmit data to and from a
memory subsystem without the need of a CPU.

S
zz A DMA Controller is a device that controls data transfers between an I/O subsystem and a memory
subsystem in the same way that a CPU does. E
zz The Central Processing Unit (CPU), memory chips, and input/output (I/O) devices are all components
R
of a conventional computer system.
zz A bus is a cable or a common channel that connects these diverse subsystems.
T

zz A bus is a communication channel used by numerous devices, rules must be created to ensure that
communication occurs appropriately.
H

zz Buses are classed as synchronous or asynchronous depending on whether or not the transactions
are regulated by a clock.
IG

zz The processor bus is the bus that is used by the processor chip’s signals.
zz Another bus is generally provided by the motherboard, which can handle extra devices.
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zz Organizations like the IEEE (Institute of Electrical and Electronics Engineers), ANSI (American
National Standards Institute), and international organisations like the ISO (International Standards
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Organization) have granted these standards formal status in some circumstances.

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zz The PCI bus is an excellent example of a system bus that arose from a desire for standardisation. It
provides functionalities located on a processor bus bit in a defined format that is not specific to any
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processor
zz SCSI bus refers to the ANSI-defined X3.131 standard bus.
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zz DMA is used by this controller to transport data packets from main memory to the device and vice
versa.

3.8 Glossary

zz Peripheral devices: It refers to input or output devices that are connected to a computer.
zz Direct Memory Access (DMA): It refers to an I/O subsystem’s ability to transmit data to and from a
memory subsystem without the need of a CPU.
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zz DMA controller: A device that controls data transfers between an I/O subsystem and a memory
subsystem in the same way that a CPU does.
zz Bus: A cable or a common channel that connects these diverse subsystems.
zz Universal Serial Bus (USB): Computer-communications synergy is at the heart of today’s information
technology revolution.
zz SCSI bus: It refers to the ANSI-defined X3.131 standard bus. Devices like discs are linked to a computer
via a 50-wire connection that may be up to 25 metres long and transport data at up to 5 megabytes
per second, according to the standard’s initial requirements.

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3.9  Self-Assessment Questions

E
V
A. Multiple Choice Questions

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1. Input or output devices that are connected to computer are called __________.
a. Input/Output subsystem

E
b. Peripheral devices

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c. Interfaces
d. Interrupt
2. How many types of modes of I/O Data Transfer?
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a. 2 b. 3
c. 4 d. 5
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3. Keyboard and mouse comes under?

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a. Input peripherals B Output peripherals

c. Input-Output peripherals d. None of these
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4. The method which offers higher speeds of I/O transfers is __________.

a. Interrupts b. Memory mapping
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c. Program-controlled I/O d. DMA

5. In memory-mapped I/O __________.
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a. The I/O devices have a separate address space

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b. The I/O devices and the memory share the same address space
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c. A part of the memory is specifically set aside for the I/O operation
d. The memory and I/O devices have an associated address space
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6. The __________ circuit is basically used to extend the processor BUS to connect devices.
a. Router b. Router
c. Bridge d. None of these
7. The ISA is an architectural standard developed by __________.
a. IBM b. AT&T Labs
c. Microsoft d. Oracle

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Computer Organization and Architecture

8. The SCSI BUS is used to connect the video devices to a processor by providing a __________.
a. Single Bus b. USB
c. SCSI d. Parallel Bus
9. Which of the following is used by the processor chip’s signals?
a. Processor bus b. SCSI bus
c. USB bus d. None of these
10. The registers of the controller are __________.

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a. 16 bit b. 32 bit
c. 64 bit d. 128 bit

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11. The main job of the interrupt system is to identify the __________ of the interrupt.

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a. signal b. device

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c. source d. peripherals
12. The hardware interrupts which can be delayed when a much high priority interrupt has occurred at

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the same time are known as __________.

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a. Non-maskable interrupt b. Maskable interrupt
c. Normal Interrupt d. None of these
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13. The interrupts that are caused by software instructions are called __________.
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a. Exception interrupts b. Normal interrupt
c. hardware interrupt. d. None of these
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14. In Daisy Chaining Priority, the device with the highest priority is placed at the __________.
a. First position b. Last position
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c. Can be placed anywhere d. Depend on device

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15. Which interrupt is unmaskable?

a. RST 5.5 b. RST 6.5
c. RST 7.5 d. Trap
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16. Which microprocessor is designed to complete the execution of the current instruction and then to
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service the interrupts?

a. 8081 b. 8082
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c. 8084 d. 8085
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17. Open-collector type circuits are generally used for __________.

a. open-drain b. Batch processing
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c. interrupt service lines. d. None of these

18. The Interrupt-request line is a __________ along which the device is allowed to send the interrupt
signal.
a. Data line b. control line
c. Address line d. None of these

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19. Which table handle stores the addresses of the interrupt handling sub-routines?
a. Interrupt-vector table b. Vector table
c. Symbol link table d. All of these
20. Interrupts initiated by an instruction is called as __________.
a. Internal b. External
c. hardware d. Software

B. Essay Type Questions

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1. The bus allows all of the devices connected to it to communicate with one another. Discuss.

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2. When a process or event requires immediate attention, hardware or software emits an interrupt
signal. What do you mean by hardware interrupt?

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3. What do you understand by Direct Memory Access (DMA)?

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4. Bus allows the various components to interact with one another. Discuss.
5. Discuss the concept of PCI bus.

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3.10  Answers AND HINTS FOR Self-Assessment Questions

A. Answers to Multiple Choice Questions

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Q. No. Answer
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1. b.  Peripheral fevices

2. b. 3
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3. a.  Input peripherals

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4. d. DMA
5. b.  The I/O devices and the memory share the same address space
6. c. Bridge
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7. a. IBM
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8. d.  Parallel bus

9. a.  Processor bus
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10. b.  32 bit

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11. c. source
12. b.  Maskable interrupt
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13. b.  Normal interrupt

14. a.  First position
15. d. Trap
16. d. 8085
17. c.  interrupt service lines.

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Computer Organization and Architecture

Q. No. Answer
18. b.  control line
19. a.  Interrupt-vector table
20. b. External

B. Hints for Essay Type Questions

1. It usually has three sets of lines for carrying address, data, and control signals. A unique set of
addresses is assigned to each I/O device. The device that recognises a certain address responds to

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the commands sent on the control lines when the processor places that address on the address line.
Refer to Section Accessing I/O Devices

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2. We said that an I/O device requests an interrupt by activating the interrupt-request bus line. Almost

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all computers have several I/O devices that can request an interrupt. As shown, a single interrupt-
request line can be utilised to service n devices. Switches to ground are used to connect all devices to

R
the line. Refer to Section Interrupts
3. Direct Memory Access (DMA) refers to an I/O subsystem’s ability to transmit data to and from a

E
memory subsystem without the need for a CPU. A DMA Controller is a device that controls data
transfers between an I/O subsystem and a memory subsystem in the same way that a CPU does.

S
Refer to Section Direct Memory Access
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4. In computer terms, a bus is a conduit that allows data to move between units or devices. It usually
has access points, which are locations where a device may tap to join the channel. The majority of
R
buses are bidirectional, meaning that devices may transmit and receive data. Refer to Section Buses
5. The PCI bus is an excellent example of a system bus that arose from a desire for standardisation.
T

It provides functionalities located on a processor bus bit in a defined format that is not specific to
any processor. The CPU sees devices linked to the PCI bus as if they were connected directly to the
H

processor bus. Refer to Section Standard I/O Interfaces

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@ 3.11  Post-Unit Reading Material

zz https://www.studocu.com/in/document/psg-college-of-technology/computer-architecture/m-
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morris-mano-solution-manual-computer-system-architecture/10775236
https://www.pvpsiddhartha.ac.in/dep_it/lecturenotes/CSA/unit-5.pdf
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zz
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3.12  Topics for Discussion Forums

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zz Discuss about Input/Output (I/O) Organisation with your friends.

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