Unit 3 Full

Prepared by Mr. S.
Murali, AP/CSE
UNIT III - I/O INTERFACING
Memory Interfacing and I/O interfacing - Parallel

communication interface – Serial communication
interface – D/A and A/D Interface - Timer –
Keyboard /display controller – Interrupt controller
– DMA controller – Programming and applications
Case studies: Traffic Light control, LED display, LCD
display, Keyboard display interface and Alarm
Controller.
Prepared by Mr. S. Murali, AP/CSE, VCET

Prepared by Mr. S. Murali, AP/CSE
Memory Interfacing and I/O interfacing
Interface is the path for communication between two

components. Interfacing is of two types
• Memory interfacing and
• I/O interfacing.
Memory interfacing:
•When executing any instruction, the microprocessor needs to

access the memory for reading instruction codes and the data
stored in the memory.
•For this, both the memory and the microprocessor requires some
signals to read from and write to registers.

•The interfacing process includes some key factors to match with

the memory requirements and microprocessor signals.
•The interfacing circuit therefore should be designed in such a way

that it matches the memory signal requirements with the signals
of the microprocessor.
IO Interfacing
-Various communication devices like the keyboard, mouse, printer,
etc. needs to interface with the microprocessor by using latches
and buffers.
This type of interfacing is known as I/O interfacing.

295
MEMORY DEVICES I/O DEVICES

Address decoding circuit:
-used to select the i/o devices or memory chip for data

transfer while executing the instructions.
Data transfer is of 2 types
Synchronous Data Transfer – if the peripherals are located

within the same computer as CPU. All peripherals work on a
common clock
Asynchronous Data Transfer – Do not require the peripherals

needs to work under common clock

I/O interfacing:
--need to transfer the data from external circuit to

microprocessor or from microprocessor to external circuit
Input device – give information to microprocessor
Output device – display information from microprocessor
I/O transfer is controlled by RD, WR and IO/M signals
I/O devices can be interfaced with microprocessor by

•Memory mapped i/o
•I/O mapped i/o

Memory Mapped I/O:
-uses the same address space to address

both memory and I/O devices.
-The memory and registers of the I/O devices are mapped to

(associated with) address values.
-When an address is accessed by the CPU, it may refer to a

portion of physical RAM, or it can instead refer to memory of
the I/O device.
-CPU instructions used to access the memory can also be

used for accessing devices.

Memory Mapped I/O:
-Each I/O device monitors the CPU's address bus and

responds to any CPU access of an address assigned to that
device, connecting the data bus to the desired
device's hardware register.
To accommodate the I/O devices, areas of the addresses used

by the CPU must be reserved for I/O and must not be
available for normal physical memory.
The reservation may be permanent, or temporary (as

achieved via bank switching).

I/O Mapped I/O:
-uses a special class of CPU instructions designed specifically

for performing I/O, such as the in and out instructions.
-Different forms of these two instructions can copy one, two

or four bytes (outb, outw and outl, respectively) between
the register and a specified I/O port of an I/O device.
-I/O devices have a separate address space from general

memory
-Because the address space for I/O is isolated from that for
main memory, this is sometimes referred to as isolated I/O.


Serial Communication Interface - USART

328

8251 takes data serially from peripheral (outside

devices) and converts into parallel data.
After converting the data into parallel form, it

transmits it to the CPU.
Similarly, it receives parallel data from microprocessor

and converts it into serial form.
After converting data into serial form, it transmits it to

outside device (peripheral).

Data bus buffer – helps in interfacing the internal data bus of

8251 to the system data bus.
Read/Write control logic –

It is a control block for overall device. It controls the overall
working by selecting the operation to be done.

DSR: Data Set Ready signal is an input signal.
DTR: Data terminal Ready is an output signal.
CTS: It is an input signal which controls the data transmit circuit.
RTS: It is an output signal which is used to set the status RTS.
TXD: It is an output signal, if its value is one, means transmitter

will transmit the data.
TXRDY: It means transmitter is ready to transmit data character.
TXEMPTY: An output signal which indicates that TXEMPTY pin has

transmitted all the data characters and transmitter is empty now.
TXC: An active-low input pin which controls the data transmission

rate of transmitted data.

RXD: An input signal which receives the data.
RXRDY: An input signal indicates that it is ready to receive the

data.
RXC: An active-low output signal which controls the data

transmission rate of received data.
SYNDET/BD: An input or output terminal. External synchronous

mode-input terminal and asynchronous mode-output terminal.

Control Register:
A register used to determine the functions of the

chip i.e. to define its I/O ports, and must be loaded
before any transmission or reception.
Data Buffer Register:
A register that holds the data to be transferred.

The control words of Block Diagram of 8251 Microcontroller are split

into two formats
1. Mode instruction – used to set the mode of oprn of 8251

2. Command instruction – used to issue the command to 8251


8251 Status Register:
In the data communication systems it is often necessary to examine the

“status” of the transmitter and receiver and to know if any error has
occurred during communication. The above mentioned information can
be known through the status register

Parallel Communication Interface – transmission 299
can take place as simultaneous bits at same time
INTEL 8255


• The 8255 chip is also called as Programmable 300
Peripheral Interface.
• The Intel’s 8255 is designed for use with Intel’s

8-bit, 16-bit and higher capability microprocessors
• The 8255 is a 40 pin integrated circuit (IC),

designed to perform a variety of interface
functions in a computer environment i.e. to
interface the CPU with its outside world such as
ADC, DAC, keyboard etc.
• It is flexible and economical.

301
PIN DIAGRAM OF 8255

8255
303
 24 input/output lines which may be

individually programmed.
 2 groups of I/O pins are named as
Group A (Port-A & Port C Upper)
Group B (Port-B & Port C Lower)
 3 ports(each port has 8 bit)
Port A lines are identified by symbols PA0-PA7
Port B lines are identified by symbols PB0-PB7
Port C lines are identified by PC0-PC7 ,
ie: PORT C UPPER(PC7-PC4) , PORT C LOWER(PC3-PC0)
Port A – can be programmed in mode 0, mode 1 and mode 2
Port B - can be programmed in mode 0 and mode 1
Port C - can be programmed in mode 0
D0 - D7: data input/output lines for the 304
device. All information read from and

written to the 8255 occurs via these 8 data
lines.
CS (Chip Select). If this line is a logical 0, the

microprocessor can read and write to the
8255.
RESET : The 8255 is placed into its reset

state if this input line is a logical 1

305
• RD : This is the input line driven by the

microprocessor and should be low to
indicate read operation to 8255.
• WR : This is an input line driven by the
microprocessor. A low on this line
indicates write operation.
• A1-A0 : These are the address input lines
and are driven by the microprocessor.

306
Control Logic
 CS signal is the master Chip Select
 A0 and A1 specify one of the two I/O Ports
CS A1 A0 Selected
0 0 0 Port A
0 0 1 Port B
0 1 0 Port C
0 1 1 Control
Register
1 X X 8255 is not
selected

313

314
Modes of Operation of 8255
 Mode 0 (Simple input/output)

 Mode 1 (Handshake mode)
 Mode 2 (Bidirectional Data Transfer)

317
a) Mode 0 (Simple Input or Output):
• Ports A and B are used as Simple I/O

Ports
• Port C as two 4-bit ports
• Features
– Outputs are latched
– Inputs are not latched
– Ports do not have handshake or
interrupt capability

Mode 1: (Input or Output with Handshake)

319
Port A - act as input or output based on D4 in control word and
upper half of port C - handshaking and control signals. (STB, IBF, OBF,
ACK)
If port c as input then
PC4 – STBA – 0 to this pin makes PA0 to PA7 is activated
PC5 – IBFA – indicating Input Buffer Full and, set to 1 when port A
contains data that not been sent to CPU and set to 0 when port A
doesn’t contain data
PC6, PC7 – send control signals to device or read status from device.
When D3 in CWR 0, it will send control signals and when D3 is 1 it reads
status

Mode 1: (Input or Output with Handshake)

319
Port A - act as input or output based on D4 in control word and
upper half of port C - handshaking and control signals. (STB, IBF, OBF,
ACK)
If port c as output then
PC7 – OBFA – indicating Output Buffer Full. 0 when port A has data to
send from buffer
PC6 – ACKA – device set 0 (as acknowledgement) when receive the data
from port A
PC4 and PC5 – serves same as PC6 and PC7 under port c as input

Mode 2: (Bidirectional Data Transfer)

319
Applies only to Group A and also PC3 – makes interrupt requests
PC4 – STBA – 0 to this pin makes PA0 to PA7 strobe into Port A
PC5 – IBFA – indicating Input Buffer Full and, set to 1 when port A
contains data that not been sent to CPU and set to 0 when port A
doesn’t contain data
PC6 - ACKA - 0 when the device is ready to accept data from PA0 – PA7
PC7 – OBFA – 0 when port A is filled with data and 1 when data are taken
by device.

321
Write a program to initialize 8255 in the configuration
below.(assume address of the CW register as 23H).
(1) Port A: output with handshake
(2) Port B: input with handshake
(3) Port CL: output (4)Port CU: input
 Solution:
1 0 1 0 1 1 1 0 = AEH
Program:
MOV AH,AEH ; LOAD CONTROL WORD
OUT 23H ; SEND CONTROL WORD

322
 Port A: Output, Port B: Output,

 Port CU: Output, Port CL: Output
Solution:
1 0 0 0 0 0 0 0 = 80H
The control word register for the above ports of Intel

8255 is 80H.

A/D and D/A Conversion

Sample and Hold circuit – to keep the analog signal constant

during the conversion
Group A – configured as input under mode 1
The conversion is initiated by PC7 pin of 8255 which makes

the converter to initiate busy signal.
When the busy signal goes down after conversion, the strobe
signal send through PC4 which makes the digital data sending
to port A.
Port B is acting as output in mode 0 under digital to analog

conversion

Analog to Digital Converter - 0809

IN0 to IN7 – input lines for sending analog signal using three
address lines A, B, C
ALE – used to load the selected address lines to ADC.

Start - Rising edge of the pulse make the internal registers of

ADC to clear and falling edge the conversion starts
OE – outputs the digital values on the output lines

Digital to Analog Converter - 0800

Threshold Control – Used to control the temperature during

the conversion (maximum 125 degree centigrade)
Compensation – avoid the oscillation in the converted analog

signal
Vref (+) and Vref (-) – used to set the positive and negative
voltage references of analog signal

8254-Programmable Interval Timer and Event

Counters
A device that marks intervals of time for both the processor

and external devices, counts events in particular time
Uses:
•To switch over between programs by generating interrupt at
particular time
•To out the signals at correct time to any I/O devices
•To measure time delay between external events
•Count the number of times an event occurs


•Clock signal is enabled when GATE signal is set as high and

the “Initial Count Register” is initialized by a value
•Counter is a component that performs count (decrements

the value) in Initial Count Register
•When the counter decrements the value to 0, the value is

displayed in Counter Out Register and when the register is 0
then OUT signal is activated
•OUT send the signal to i/o devices (indicating time is end) or

interrupt controller to generate interrupt request to stop the
operation since time ends.

E.g. – 8254 (Programmable Interval Timer)

•Consists of three counters (Counter 0, 1 and 2) with

respective CLK, GATE and OUT pins
•Each counter is having

•Control and Status register
•CR - Counter Register (Initial Count Register)
•CE - Counter Element (Counter)
•OL - Output Latch (Counter Output Register)
•CR, CE and OL are 16 bit registers (divided into two 8 bit

registers – MSB and LSB)
•Registers can be accessed by using CS, RD, WR, A1 and A0

pins


Modes of 8254
• Mode 0 : Interrupt on Terminal Count

• Mode 1 : Hardware Retriggerable One-Shot
• Mode 2 : Periodic Interval Timer
• Mode 3 : Square Wave Mode/Generator
• Mode 4 : Software Triggered Strobe
• Mode 5 : Hardware Triggered Strobe


•Needs to read the value of the counter without disturbing

the count in progress and it is done by
•A simple read operation

•Counter Latch command
•Read back command
A simple read operation:
-To read the Counter, which is selected with the A1, A0 inputs,
the CLK input of the selected Counter must be inhibited by
using either the GATE input or external logic.

Counter Latch command
The selected Counter's output latch (OL) latches the count at

the time the Counter Latch Command is received.
This count is held in the latch register until it is read by the

CPU (or until the Counter is reprogrammed).

Read Back command
-checks the count value and NULL count flag of selected

counters.
-used to latch multiple counter output latches (OL) by setting

the COUNT bit D5 = 0 and selecting the desired counter(s).

Status Register
-read-back command may also be used to latch status

information of selected counter(s) by setting STATUS bit D4 =
0.

8279 - Keyboard and Display Controller
-For small systems, keyboard is simple and through which

data, memory addresses and machine code is entered in
hexadecimal form
-Apart from alphanumeric keys, some functional keys to enter

and monitor control commands.
Mechanical Contact Keyboard - Design:
-Key switches organized in 8X8 matrix form
-When a key is depressed, the corresponding row and column

are shorted to form path

Keyboard and Display
-By detecting the row and column positions of the contact,

the code word of the key is determined (0’s and 1’s)
Keyboard scanning – Output ports sends 0 to row 0 and 1 to

all other rows and check column lines. If 0 is detected in any
column then the code word made the path is found. If no 0 is
found then the same is repeated for next row and so on
Problems – When a key is pressed, it bounces for certain time

and then only made path by closed position. The duration of
bouncing is less than 10 ms. Contact closures due to bouncing
must be discarded to prevent false key detection and this
operation is called debouncing eliminated by s/w or h/w

Keyboard and Display
Display Design:
-More devices are available for displaying and 7 segment LED

display is used for hexadecimal digit display.
•A digit in seven-segment code is fed to input
through ‘g’ and ‘dp’
•i/p can be represented as low or high

depending on whether display is common
anode type (segments are connected to
power supply) or common cathode type
(segments are connected to ground)

8279 – Keyboard / Display Controller

8279
Data Buffer Register – to store the data from the data bus
Control register – modes of operation of 8279
Timing register – used to maintain the bouncing time during a

key pressed
16 byte display memory – stores the data of the key pressed
8-byte FIFO sensor memory – stores the identified code word

of the key pressed
SL3-SL0: Scan line outputs that scans both the keyboard and
displays.
8279
Scan counter – contains the details of the scan lines SL0 to

SL3
RL7-RL0: Return lines (column lines) are inputs used to sense

key depression in the keyboard matrix.
OUT A3-A0/B3-B0: Outputs that sends data to the most

significant/least significant nibble of display
IRQ: Interrupt request, becomes 1 when a key is pressed, data

is available.
CN/ST: Control/strobe, connected to the control key on the

keyboard
377

375
 Keyboard section
 Display section
 Scan section
 CPU interface section

378
 The keyboard section consists of 8 return

lines RL0 - RL7 that can be used to form the
columns of a keyboard matrix.
 It has two additional input : shift and
control/strobe. The keys are automatically
debounced.
 The two operating modes of keyboard
section are 2-key lockout and N-key rollover.

378
 The keyboard section consists of 8 return

lines RL0 - RL7 that can be used to form the
columns of a keyboard matrix.
 It has two additional input : shift and
control/strobe. The keys are automatically
debounced.
 The two operating modes of keyboard
section are 2-key lockout and N-key rollover.

380
 The display section has eight output lines

divided into two groups A0-A3 and B0-B3.
 The output lines can be used either as a
single group of eight lines or as two groups
of four lines, in conjunction with the scan
lines for a multiplexed display.
 The output lines are connected to the 7-
segment LEDs.

381
 The display can be blanked by BD (low) line.
 The display section consists of 16 x 8 display

RAM. The CPU can read from or write into
any location of the display RAM.

382
 The scan section has a scan counter and four scan

lines, SL0 to SL3.
 In decoded scan mode, the counter internally
decodes least significant 2 bits
 In encoded scan mode, the counter provides
binary count, and so an external decoder
should be used to convert the binary count to
decoded output.
 The scan lines are common for keyboard and
display.

383
 The CPU interface section takes care of data

transfer between 8279 and the processor.
 This section has eight bidirectional data
lines DB0 to DB7 for data transfer between
8279 and CPU.
 It requires two internal address A =0 for
selecting data buffer and A = 1 for selecting
control register of8279.

384
 The control signals WR (low), RD (low), CS

(low) and A0 are used for read/write to
8279.
 It has an interrupt request line IRQ, for
interrupt driven data transfer with processor.
 The 8279 require an internal clock
frequency of 100 kHz. This can be obtained
by dividing the input clock by an internal
prescaler.

385
All the command words or status words are written or

read with A0 = 1 and CS = 0 to or from 8279.
a) Keyboard Display Mode Set : The format of the command word to select different
modes of operation of 8279 is given below with its bit definitions.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 0 D D K K K

386
SENSOR MATRIX
SENSOR MATRIX

387
B) Programmable clock :
The clock for operation of 8279 is obtained by

dividing the external clock input signal by a
programmable constant called prescaler.
 PPPPP is a 5-bit binary constant.
The input frequency is divided by a decimal constant
ranging from 2 to 31, decided by the bits of an internal
prescaler, PPPPP.
D7 D6 D5 D4 D3 D2 D1 D0
0 0 1 P P P P P

c) Read FIFO / Sensor RAM : The format of this command is given 388
below.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 0 AI X A A A
AI – Auto Increment Flag

AAA – Address pointer to 8 bit FIFO RAM
X- Don’t care
This word is written to set up 8279 for reading FIFO/ sensor RAM.
In scanned keyboard mode, AI and AAA bits are of no use. The
8279 will automatically drive data bus for each subsequent read, in
the same sequence, in which the data was entered.
In sensor matrix mode, the bits AAA select one of the 8 rows of
RAM.
If AI flag is set, each successive read will be from the subsequent
RAM location.

389
d) Read Display RAM :

This command enables a programmer to read the display RAM data.
D7 D6 D5 D4 D3 D2 D1 D0
0 1 1 AI A A A A
The CPU writes this command word to 8279 to prepare it for

display RAM read operation.
AI is auto increment flag and AAAA, the 4-bit address points to
the 16-byte display RAM that is to be read.
If AI=1, the address will be automatically, incremented after
each read or write to the Display RAM.
The same address counter is used for reading and writing.

390
d) Write Display RAM :

This command enables a programmer to write the display RAM data.
D7 D6 D5 D4 D3 D2 D1 D0
1 0 0 AI A A A A
AI – Auto increment Flag.

AAAA – 4 bit address for 16-bit display RAM to be written

391
g) Clear Display RAM :
D7 D6 D5 D4 D3 D2 D1 D0
1 1 0 CD2 CD1 CD0 CF CA
CD2 CD1 CD0
0X - All zeros ( x don’t care ) AB=00

ENABLES CLEAR DISPLAY 10 - A3-A0 =2 (0010) and B3-B0=00 (0000)
WHEN CD2=1 11 - All ones (AB =FF), i.e. clear RAM
• CD2 must be 1 for enabling the clear display command.
• If CD2 = 0, the clear display command is invoked by setting
CA(CLEAR ALL) =1 and maintaining CD1, CD0 bits exactly same
as above.
• If CF(CLEAR FIFO RAM STATUS) =1, FIFO status is cleared and
IRQ line is pulled down and the sensor RAM pointer is set to row
0.
•If CA=1, this combines the effect of CD and CF bits.

392
h) End Interrupt / Error mode Set :

D7 D6 D5 D4 D3 D2 D1 D0
1 1 1 E X X X 1
E- Error mode
X- don’t care
For the sensor matrix mode, this command lowers the

IRQ line and enables further writing into the RAM.
Otherwise, if a change in sensor value is detected, IRQ
goes high that inhibits writing in the sensor RAM.
 For N-Key roll over mode, if the E bit is programmed to
be ‘1’, the 8279 operates in special Error mode

8259 – Programmable Interrupt Controller
-simplify the implementation of the interrupt interface in

microcomputer systems
-28 pins IC and programmable using for variety of applications
-eight vectored priority encoded interrupts to the

microprocessor.
-Can able to expand up to 64 interrupt request inputs such a

way that 8 acts as slaves and 1 acts as master
-If any interrupt means slaves will send request to master

which in turn sends to processor

-8 interrupt lines IR0 to IR7

8259 – Programmable Interrupt Controller

-Data bus buffer, Read/Write logic and Control logic interface with the main
microprocessor
Interrupt Request Register – accepts and store the actual interrupt

requests from external interrupting devices
In Service Register – store the information that are serviced currently by

the processor
-acts as buffer between IRR and 8086 processor
Priority Resolver – determines the priorities (different schemes) of the

interrupts in IRR and the highest priority interrupt will send into the ISR to
get serviced
Interrupt Mask Register - used to disable (Mask) or enable (Unmask)

individual interrupt request inputs.
Cascade Buffer/Comparator – cascading 8259 in master-slave

configuration


Working of Master – Slave Concept

8259 – Command Words:
Two types of command words
Initialization Command Words – used to initialize 8259 before

starting operation
Operational Command Words – commands the 8259 to

operate in various modes like
•Fully nested mode

•Rotating Priority mode
•Special mask mode
•Polled mode
OCW can be written at anytime in 8259 after initialization

8259 – Command Words:
Four initialization command

words – ICW1, ICW2, ICW3,
ICW4
8259 – single mode – ICW1,

ICW2 is programmed and if
need ICW4
8259 – cascade mode – ICW1,

ICW2, ICW3 is programmed
and if need ICW4


Level Triggered - circuit will become active when the gating or

clock pulse is on a particular level.
Edge Triggered - circuit becomes active at negative or positive

edge of the clock signal

ICW3

AUTO EOI – Automatic End of Interrupt – 8259 will perform EOI

operation automatically at the trailing edge of the last INTA pulse

Modes of 8259
Fully Nested mode – all request are arranged in highest to lowest

order and it is default mode
Special Fully Nested mode - When an interrupt request from a

certain slave is in service, this slave can further send requests to
the master.
Automatic Rotating mode - a device after being serviced receives

the lowest priority
Specific Rotating - user can select any IR as lowest priority and

thus fixing all priorities. E.g. IR7 set as least means, next higher
priority is IR6 and then IR5 so on

DMA Controller - - 8237

•General data transfer is done by CPU and cycles get wasted.
•Direct Memory Access (DMA) can access the memory directly to

transfer data without CPU need and supports block transfer
• For transferring data without disturbing CPU and thus to save cycles of
CPU
•DMA transfer data directly to/from memory without any interference

from the CPU.
•DMA requests the CPU for bus access using local bus request input i.e.
HOLD in minimum mode.

DMA Controller
•In maximum mode of the microprocessor RQ/GT pin is used as bus
request input.
•On receiving the HLDA signal (in minimum mode) or RQ/GT signal (in
maximum mode) from the CPU, the requesting devices gets the access
of the bus
•Address Register – stores the source and destination address of the

data to be transferred
•Byte Count Register – stores the number of bytes to be transferred
•Mode Register – indicates the type of mode in the data is transferred

DMA Controller
DMA works in 4 modes
• Single mode – suitable for transferring one byte in one clock cycles and
if transferred completed then DMS becomes idle till the cycle ends.
•Block mode – suitable for block transfer of data
•Demand Transfer mode – whenever needed DMA transfers the data

i.e. in demand it transfers
•Cascade mode – if multiple DMA controllers involves in transfer. In this

one can acts as master and others are slaves

DMA Controller
Mask Flag – indicates which channel is using for transfer the data
CR (Command Register): Programs the operation of the controller
•Current Address register – stores the address where the data is

transferred currently (changes during transferring process)
•Base Address Register – stores the starting address of the block which
needs to be transferred.
•Base byte count register – store the total bytes needs to be transferred
•Current byte count register – stores the bytes that are transferring
currently



MR (Mode Register): Programs the mode of operation for a

channel (one for each channel).

RR (Request Register): Used to request DMA transfer via

software (memory-to-memory transfers)

MR (Mask Register) - sets or clears the channel mask to

disable or enable particular DMA channels.

SR (Status Register): Shows the status of each DMA channel

8237 Software commands

Unit 3 Full

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Unit 3 Full

Uploaded by

Copyright:

Available Formats

Prepared by Mr. S.

UNIT III - I/O INTERFACING

Memory Interfacing and I/O interfacing - Parallel

Prepared by Mr. S. Murali, AP/CSE, VCET

Memory Interfacing and I/O interfacing

Interface is the path for communication between two

•When executing any instruction, the microprocessor needs to

Prepared by Mr. S. Murali, AP/CSE, VCET

Memory Interfacing and I/O interfacing

•The interfacing process includes some key factors to match with

•The interfacing circuit therefore should be designed in such a way

This type of interfacing is known as I/O interfacing.

Prepared by Mr. S. Murali, AP/CSE, VCET

MEMORY DEVICES I/O DEVICES

Prepared by Mr. S. Murali, AP/CSE, VCET

Memory Interfacing and I/O interfacing

Address decoding circuit:

-used to select the i/o devices or memory chip for data

Data transfer is of 2 types

Synchronous Data Transfer – if the peripherals are located

Asynchronous Data Transfer – Do not require the peripherals

Prepared by Mr. S. Murali, AP/CSE, VCET

--need to transfer the data from external circuit to

Input device – give information to microprocessor

Output device – display information from microprocessor

I/O transfer is controlled by RD, WR and IO/M signals

I/O devices can be interfaced with microprocessor by

Prepared by Mr. S. Murali, AP/CSE, VCET

Memory Mapped I/O:

-uses the same address space to address

-The memory and registers of the I/O devices are mapped to

-When an address is accessed by the CPU, it may refer to a

-CPU instructions used to access the memory can also be

Prepared by Mr. S. Murali, AP/CSE, VCET

Memory Mapped I/O:

-Each I/O device monitors the CPU's address bus and

To accommodate the I/O devices, areas of the addresses used

The reservation may be permanent, or temporary (as

Prepared by Mr. S. Murali, AP/CSE, VCET

I/O Mapped I/O:

-uses a special class of CPU instructions designed specifically

-Different forms of these two instructions can copy one, two

-I/O devices have a separate address space from general

Prepared by Mr. S. Murali, AP/CSE, VCET

Prepared by Mr. S. Murali, AP/CSE, VCET

Serial Communication Interface - USART

Prepared by Mr. S. Murali, AP/CSE, VCET

Prepared by Mr. S. Murali, AP/CSE, VCET

8251 takes data serially from peripheral (outside

After converting the data into parallel form, it

Similarly, it receives parallel data from microprocessor

After converting data into serial form, it transmits it to

Prepared by Mr. S. Murali, AP/CSE, VCET

Data bus buffer – helps in interfacing the internal data bus of

Read/Write control logic –

Prepared by Mr. S. Murali, AP/CSE, VCET

DSR: Data Set Ready signal is an input signal.

DTR: Data terminal Ready is an output signal.

CTS: It is an input signal which controls the data transmit circuit.

RTS: It is an output signal which is used to set the status RTS.

TXD: It is an output signal, if its value is one, means transmitter

TXRDY: It means transmitter is ready to transmit data character.

TXEMPTY: An output signal which indicates that TXEMPTY pin has