I/O Interfacing

Prepared by

Dr. Utpal Biswas

Professor & Head
Department of Computer Science & Engineering

University Of Kalyani
Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Introduction
 We have already discussed how to interface memory with
microprocessor.
 Now our microprocessor design will be completed if we can
interface input/output (I/O) devices with it.
 Example of input devices is keyboard or simply a switch.
 Example of output device is seven-segment display or simply
one LED.

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
I/O Port
 I/O devices are not equipped with then necessary logic circuits and
properties needed for direct interfacing with the system bus as Memory
chip does. These properties are:
 Device Selection Logic: A memory location can be selected by
placing address on the address bus as memory chip has got on chip
decoder. These are not present in I/O Devices.
 Control Signal: A memory chip has got READ/WRITE and other
control signals. These are not equipped in I/O Devices.

 Because of this reason they are usually interfaced through some extra
hardware circuits knows as I/O ports.

 
𝜇𝑝 PORT I/O

Memory

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
I/O Port (Cont.)
I/O Port

  AD
  7
Buffer
AD0 or Latch

Enable

A15 Decoder Address

Decode I/O
processor A8
Pulse

82 Control Signal
IO/ ´ / 𝐼𝑂𝑊
05  𝐼𝑂𝑅 ´

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Expected Properties of I/O Ports
 An I/O Port is expected to have the following properties:
i. Device selection Logic. The device selection logic is essential for
selection of the desired I/O device.
ii. Data Buffer. I/O devices may supply or receive data for very brief
duration and at the time instantly totally unrelated to the MPU
clock. Buffer register must be provided to temporarily hold the data
either from I/O port or the MPU.
iii. Bus Drivers. Since many I/O devices may be physically connected
to the system bus and only one had to be logically connected at a
particular time instant, tri-state buffers should be provided to
logically disconnect unreferenced I/O devices.
iv. Status FF/registers. Provision should be made to maintain the
status of data transfer using flag bits or registers.
v. Control lines. The port should be equipped with suitable input and
output control lines for the implementation of asynchronous and
Interrupt driven mode of data transfer (To be discussed later).

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Output Interfacing
 Absolute decoding. All eight lines are decoded to generate one unique
output pulse.
AD7 Vcc
A15 .
Latch
. .
. AD0 .
A8 Enable
Address is 01H
´
𝐼𝑂𝑊
   
 Linear – select decoding. The output port can be selected by using one-
address line. As a result device has multiple address.
AD7
. Vcc
Latch
.
AD0 .
A8 Enable Address = 00, 02, …, FEH etc.
´
𝐼𝑂𝑊
   

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Input Interfacing
 An input port and an output port can have the I/O port address.
 The ports are differentiate by control signals.

AD7
A15 .
Buffer
. .
. AD0 .
A8 Enable

  ´R  
𝐼𝑂
 Address: FFH

i. Buffer
ii. Data flow direction is changed

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
I/O Interfacing

I/O Mapped I/O

(IN,OUT)
Hardware part
Memory Mapped
I/O (MOV, LDA,
STACK)

I/O Interfacing Synchronous

Programmed I/O Asynchronous

Software part

DMA Interrupt Driven

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
I/O Mapped I/O
  In this scheme I/O devices are considered distinct devices from memory.
So memory address space and I/O address space is different.
 I/O Mapper I/O scheme is possible if microprocessor is equipped with
IO/ line.
 Only 8-lines (either lower byte or higher byte) are decoded. Same
information is duplicated on the higher order address byte and lower
order address byte. Higher order address byte is preferred because no
demultiplexing is required with this.
 So, 28 = 265 input devices and 256 output devices can be accessed with
the help of 8085 microprocessor. Same address can be assigned to one
input as well as one output device. They will be differentiated by the
signal or .
 In this scheme we have separate I/O instructions IN port, OUT port.

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Programmed Data Transfer
 In the programmed data transfer scheme, the data transfer takes place
under the control of a program residing in the main memory of the
microcomputer system.
 The programmed data transfer is inherently slow and suitable for a small
number of bytes of data transfer with respectively slow peripherals.

Modes of
Programmed
Data Transfer

Synchronous Asynchronous Interrupt Driven

Mode Mode Mode

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Asynchronous Mode
 Used when:
o Whenever the timing characteristic of an I/O device is unpredictable,
the asynchronous method may be used.
 Basic Concept:
o The microprocessor initiates data transfer by requesting the device to
get ready and then goes on checking its status.
o The I/O instruction is executed only when the I/O device is ready to
accept or supply data.
o So each data transfer is preceded by a “request ready” signal
generated by the microprocessor.
o This method is known as handshaking mode of data transfer as it
resembles the back-and-forth movement of hands involved in
handshaking, to co-ordinate the data transfer.

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Asynchronous Mode

Start  Advantage and Disadvantage:

o The asynchronous mode is ideal for
Send get ready reconciling the timing differences
signal to the I/O between the microprocessor and I/O
devices
devices.
o However, an important disadvantage
Is device No is that a lot of precious
ready ? microprocessor time is wasted
during the looping to check the I/O
Yes device status. The wastage of the
Execute I/O microprocessor time may be
instructions prohibitive or impractical in many
situations.

Stop

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Programmed Input
 When the microprocessor is ready to input a word, it sends a high
“start” bit to the I/O.
 When the device has the data ready for transfer, it sends a high “status”
bit.
 Until the “status” bit is high, the microprocessor waits: As soon as the
“status” bit goes high, the CPU inputs 1 byte of data.
I/O
Bit 6
/8 PORT 10H Start

Micro Bit 7
/8 PORT 11H Status
processor

/8 PORT 12H /8 DATA

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Write a software to input 256 bytes and store then at
address 2000H through 20FFH
LXI H,2000H Initialize HL pair
MVI C, 00H Initialized counter

LOOP MVI A,40H Set “start” bit

1. Get ready signal
OUT 10H Send high “start” bit

WAIT IN 11H Get “status” bit

ANI 80H Isolate “status” bit 2. Check status

JZ WAIT Wait if device is not working

IN 12H Input data

3. I/O Operation
MOV M, A Store data

MVI A,00H Reset “start” bit

4. Reset
OUT 10H Send low start bit

INX H Update HL pointer

DCR C Count down

JNZ LOOP Go back if not finished

HLT Stop

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Programmed Output
 When the CPU (microprocessor) is ready, it will latch the data into port
12H. Then, the microprocessor sends a high START bit to indicate that
valid data is waiting for transfer. After the peripheral device has loaded
the data, it returns a high STATUS bit.
Peripheral
Bit 6
/8 PORT 10H Start

Micro Bit 7
/8 PORT 11H Status
processor

/8 PORT 12H /8 DATA

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Write a software to input 256 bytes from memory
locations 2000H to 20FFH.
LXI H,2000H
Initialization
MVI C, 00H

LOOP MVI A,M

Data is latched in the port by
microprocessor.
OUT 12H

MVI A, 40H
Indication that data is ready
OUT 10H

WAIT IN 11H
Wait until the data is received by the
ANI 80H
peripheral.
JZ WAIT

MVI A,00H
Reset
OUT 10H

INX H

DCR C

JNZ LOOP

HLT

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Synchronous Mode
 Used when:
o The I/O device is speed compatible with the microprocessor.
o The synchronous mode can be applied to slow I/O devices if timing
characteristics of these devices are preciously known.

 Basic Concept:
o In this case, the data transfer is initiated by requesting the I/O
devices to get ready and then the microprocessor waits for some
predetermined time, usually by generating a delay, and then executes
the I/O instruction to complete the data transfer.

 Advantages and disadvantages:

o The synchronous mode is very simple to implement.
o However, I/O devices with known timing characteristics or speed-
compatible with microprocessor seldom exist

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Synchronous Mode

Start Start

Send get ready

Execute I/O signal to the I/O
instructions devices

Generate Delay
Stop

Speed Compatible with MPU

Execute I/O
instructions

Stop

I/O with known speed characteristics

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Interrupt Driven Mode
 To overcome the drawbacks of the two preceding data transfer mode, yet
another programmed data transfer scheme called interrupt driven mode
has been designed.
 The basic philosophy of this method is that, the processor initiates data
transfer by requesting the device “to get ready” and then go on executing
its original program instead of wasting its time by continuously
monitoring the status of the I/O device.
 Whenever the device is ready to accept or supply data, it informs the
processor through some special control line known as interrupt line.
 In response to this, the processor completes the execution of the current
instruction.
 Then instead of executing the next instruction, it saves the PC (and other
registers as determined by the architecture of the microprocessor) in stack
and braches to predetermined location, which is the starting address of a
subroutine called interrupt subroutine (ISS).

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
 Interrupt Driven Mode
Start Start
ISS

I/O receives Send get ready signal to the

GET READY I/O devices Push processor
status in STACK

Fetch and Execute next

instruction
Execute I/O
instruction
INT
from I/O No
Is Interrupt
line high ? Restore
processor Status
Yes
Save PC in STACK and
Return
Jump to ISS starting address

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Interrupt Driven Mode
 The ISS saves the processor status on the stack, completes the data
transfer with the I/O responsible for interrupt, restore the processor status
and then returns to the original program that the microprocessor was
executing prior to the Interupt.

 Advantages and disadvantages:

o In this case, the time needed by the I/O device to get ready after
receiving the “get ready” is utilized by the microprocessor.

o Instead of being initiated by the microprocessor the data transfer may

also be initiated by the I/O device. This is not possible in case of
other programmed I/O.
o However the microprocessor incurs some overheat in storing and
restoring the processor status to and from the stack.

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Direct memory Access (DMA)
 In all the above cases data is transferred from I/O device to memory via
microprocessor accumulated and vice versa using software instructions.
 This makes the programmed I/O data transferred between memory and
fast I/O device, the overhead incurred by this slow process may be
prohibited.
 To overcome this problem, another data transfer scheme is designed
which is known as direct memory access (DMA).
 The main idea underlying this method is that, the microprocessor is
dissociated from the data transfer process by tristating its address bus,
data bus and memory and I/O control lines.
 A direct link is established between the memory and I/O device, and
data transfer is controlled by and external circuit known as DMA
Controller.

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Direct memory Access (DMA)
 To facilitate DMA the microprocessor must be equipped with the
following features:
i. An input control line, through which the I/O device, via the DMA
Controller, requests the microprocessor for DMA data transfer.
ii. An output control line, through which the microprocessor informs
the DMA grant.
iii. The microprocessor must be able to tristate the address, data and
necessary control lines throughout the DMA data transfer duration.

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Direct memory Access (DMA)
 The DMA controller must also perform the following functions:
i. Interface the microcontroller buses with the I/O.
ii. Generate DMA request signal.
iii. In response to the DMA grant signal from the microprocessor, it
must control the address bus and the control lines needed for the
transfer.
iv. It must hold information about the number of bytes to be transfer,
along with the staring address of the data in memory, so that it can
sequentially generate the RAM address one by one and can
withdraw the DMA request when the last byte of data transfer is
over.

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Direct memory Access (DMA)
Start

I/O device gets ready

Initialize DMA Controller and sends DMA request
to the DMA Controller
Send get ready signal to the
I/O devices
DMA Controller sends
DMA request to the
Fetch and Execute next MPU
instruction

No Is DMA Data transfer in DMA

request
mode continues till the
active?
assigned block is
Yes transferred and then the
Generate DMA Grant signal DMA controller
and tristate the buses withdraws the DMA
request

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Cycle Stealing DMA mode
Start
Initialize data byte count reg.
and memory address reg.
 In this case, one or two bytes of data are
transferred on being granted the DMA by
the MPU and then withdraws the DMA
request.

Place DMA request

No
Is DMA No
request
active? Is count =
0?
Yes
Transfer one byte of data Yes
Interrupt MPU
Update count and addr. reg.
Go idle

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017
Block DMA mode or Burst DMA Mode
From the previous program instruction

Input No Enter halt state and remain there

Device
until operator process started
ready ?

Yes

Input No  In this case, once initiated, the data

Device transfer process does not stop until the
ready ? complete block is transferred.

Yes
Send an initiate read command to
the device along with memory
starting address and total number
of bytes to be transferred

Continue execution of the rest of the program

Dr. Utpal Biswas, Dept. of Comp. Sc. & Engg., University of Kalyani, Kalyani, India, 2017