UNIT-IV

HDL for Finite state machines code:

-> Design of a sequence detector(0110)(mealy)
module seq_detector(x,clk,reset,z);
input x,clk,reset;
output reg z;
parameters s0=0,s1=1,s2=2,s3=3;
reg [0:1] ps,ns;

always @(ps,x)
case(ps)
s0:begin
z=x?0:0;
ns=x?s0:s1;
end
s1:begin
z=x?0:0;
ns=x?s2:s1;
end
s2:begin
z=x?0:0;
testbench code:
ns=x?s3:s1;
end
module test_sequence;
s3:begin
reg x,clk,reset;
z=x?0:1;
wire z;
ns=x?s0:s1;
seq_detector seq(x,clk,reset,z);
end
intial
endcase
begin
endmodule
$dumpfile("sequence.vcd");
$dumpvars(0,test_sequence);
clk=1'b0;
reset=1'b1;
#15 reset=1'b0;
end
always #5 clk= clk
intial
#10 x=0; #10 x=0; #10 x=1;
#10 x=1;..............
end
endmodule
->Design of sequence detector(1011)using moore model
given 1011 here n=4, r no of states=n+1=5

code:

module seq_detector(x,clk,reset,z); 0 1 1
input x,clk; 0
input reset; 1 0 1 1
s0/0 s1/0 s2/0 s3/0 s4/1
output z;
parameter s0=3'b000,s1=3'b001,
0 0
s2=3'b011,s3=3'b010,
s4=3'b110;
reg[0:2] cs,ns;
always @(cs)
always @(posedge clk,posedge reset) begin
begin case(cs)
if (reset==1) s0:z=0;
cs=s0; s1:z=0;
else s2:z=0;
cs=ns; s3:z=0;
end s4:z=1;
always @(cs,x) endcase
begin end
case(cs) endmodule
s0:begin
if(x==1)
ns=s1; testbench:
else
ns=s0; module tb_seqdetector:
end reg x,clk,reset;
s1:begin wire z;
if(x==0)
ns=s2; seq_detector SEQ(.x(x),.clk(clk),.reset(reset),.z(z))
else
ns=s1; intial
end begin
s2:begin clk=0;
if(x==0) forever #5 clk= clk
ns=s0; end
else
ns=s3; intial
end begin
s3:begin x=0;
if(x==0) reset=1;
ns=s2; #30 reset=0;
else #40 x=1; #10 x=0; #10 x=1;#10 x=0;
ns=s4; #10 x=1;#10 x=0;...........
end end
s4:begin endmodule
if(x==0)
ns=s2;
else
ns=s1;
end
default:ns=s0;
endcase
end
$dumpvars and $dumpfile Verilog

$dumpfile

The $dumpfile is used to dump the changes in the values of nets and registers in a file
that is named as its argument. For example

$dumpfile("test.vcd");

will dump the changes in a file named test.vcd.

The changes are recorded in a file called VCD file that stands for value change dump
A VCD (value change dump) stores all the information about value changes.
We can not have more than one $dumpfile statements in verilog simulation.
But what exactly are we going to dump in this file ? Thhis is specified by $dumpvars
the declaration onf $dumpfile must come before the $dumpvars or any other system
tasks that specifies dump.

$dumpvars

The $dumpvars is used to specify which variables are to be dumped

( in the file mentioned by $dumpfile).
The simplest way to use it is without any argument.

$dumpvars;

In this case, it dumps ALL variables in the current testbench module and in all other
modules instantiated by it
The general syntax of the $dumpvars include two arguments as in

$dumpvars(<levels> <, <module_or_variable>>* );

We basically can specify which modules , and which variables in modules will be dumped.
The simplest way to use this is to set the level to 0 and module name as the top module
( typically the top testbench module) as in

$dumpvars(0, toptestbench_module);

When level is set to 0, and only the module name is specified,

it dumps ALL the variables of that module and all the variables in ALL lower level modules
instantiated by this top module.
Design of serial adder using moore

module seial_add(x,y,clk,reset,cout,sum);
input x,y,clk,reset;
output cout,sum; 00
parameter A=2'b00,B=2'b01,C=2b'10,D=2b'11; 01.10
A/00 B/01
reg[1:0] ps,ns; 00
always @(ps,x,y) 11 11 00 00
begin 11
case(ps) C/10 D/11 01,10
A:begin 01,10
11
if(x==1'b0 && y==1b'0) 01,10
ns=A;
else if(x==1'b1 && y==1b'1)
ns=c;
else
ns=B;
end
B:begin
if(x==1b'0 && y==1b'0) assign sum=(ps==B//ps==D) ? 1b'1:1b'0
ns=A;
else if(x==1b'1 && y==1b'1) assign cout=(ps==c//ps==D)?1b'1:1b'0;
ns=C;
else endmodule
ns=B;
end
C:begin
if(x==1b'0 && y==1b'0)
ns=B;
else if(x==1b'1 && y==1b'1)
ns=D;
else
ns=C;
end
D:begin
if(x==1b'0 && y==1b'0)
ns=B;
else if(x==1b'1 && y==1b'1)
ns=D;
else
ns=C;
end
default:ns=A;
endcase
end

always @(posedge clk,posedge reset)

begin
if(reset==1b'1)
ps=A;
else
ps=ns;
end
Design of serial adder using mealy
reset
module serial_addr(a,b,cin,clk,reset,sum,ns) 11/0
input a,b,cin; 00/0, 01/0,
input clk,reset; S0 S1 10/0,
01/1,
output reg sum,ns; 10/1 11/1.
reg cst; 00/1
parameter s0=1b'0,s1=1b'1;
intial
cst=cin

always @(posedge clk)

begin
case(cst)
s0:begin
sum=a^b;
if(a&b)
ns=s1; always @(posedge clk)
else begin
ns=cst; if(reset)
end cst=s0;
s1:begin else
sum=a^b; cst=ns;
if( a& b) end
ns=s0; endmodule
else
ns=cst;
end
default:ns=s0;
endcase
end
Design of serial parity detector

1/1
0/0 odd 0/1
module parity_gen(x,clk,z) even
input x,clk;
1/0
output reg z;
reg even_odd;
parameter even=0,0dd=1; testbench code:

always @(posedge clk) module test_parity;

case(even_odd) reg x,clk;
even:even_odd<=x?odd:even; wire z;
odd:even_odd<=x?even:odd; parity_gen PAR(x,clk,z);
default:even_odd<=even; intial
endcase begin
dumpfile("parity,vcd");
always@(even_odd) dumpvars(0,test_parity);
case(even_odd) clk=1'b0;
even:z=0; end
odd:z=1; always #5 clk= clk
endcase intial
endmodule begin
#2 x=0; #10 x=1; #10 x=1; #10 x=1......
#10 finsh
end
endmodule
 Example: There are three lamps red,green and yellow,that should glow cyclically with a
fixed time interval.

sol:
r module cyclic_lamp(clk,light);
clk g input clk;
y output reg[0:2] light;
parameter s0=0,s1=1,s2=2;
s0 parameter red=3'b100,green=3'b010
red yellow=3'b001;
reg[0:1] state;

green yellow s2 s1 always @(posedge clk)

case(state)
s0:state<=s1;
s0-red,s1-green,s2-yellow
s1:state<=s2;
s2:state<=s0;
testbench: default:state<=s0;
endcase
module ts_lamp; always @(state)
reg clk; case(state)
wire[0:2] light; s0:light=red;
cylic_lamp lmp(clk,light); s1:light=green;
always #5 clk= clk s2:light=yellow;
intial defalut:light=red;
begin endcase
clk=1'b0; endmodule
#1000 finish;
end
intial
begin
dumpfile("cyclic.vcd");
dumpvars(0,ts_lamp);
monitor( time,"rgy:%b,light)
end
endmodule
Example: Moore type FSM that reads a binary sequence x and set z=1 if either 110 or 101
pattern (with overlaps) is detected.the state diagram is shown below

module moore(clk,clr,x,z);
input clk,clr,x;
A B C D
output reg z;
reg[2:0] ps,ns;
parameter A=3'b000, B=3'b001,C=3'b010,
D=3'b011,E=3'b100,F=3'b101;
E F
//define next state combinational logic

always @(ps,x)
case(ps)
A: if(x) ns=B;
else ns=A;
B: if(x) ns=C;
else ns=E; //define state update sequential logic
C: if(x) ns=C;
else ns=D; always @(negedge clr,posedge clk)
D: if(x) ns=F; if(!clr) ps=A;
else ns=A; else ps=ns;
E: if(x) ns=F;
else ns=A; //define ouput combinational logic
F: if(x) ns=c; always @(ps)
else ns=E; if(ps==D// ps==F) z=1;
default:ns=3'bxxx; else z=0;
endcase
endmodule
Example:Mealy type FSM that detects 110 and 101(with overlaps) and set z=1

B
module design(clk,clr,x,z)
input clk,clr,x;
output reg z; A C
reg [1:0] ps,ns;
parameter A=2'b00,B=2'b01,C=2'b10,D=2'b11;
D
//define next state & o/p combinational logic
always @(ps,x)
case(ps)
A:if(x)
begin ns=B; z=0; end
else
begin ns=A; z=0; end

B:if(x)
begin ns=C; z=0; end
else
begin ns=D; z=0; end

C:if(x)
begin ns=C; z=0; end B
else
begin ns=D; z=1; end
A C
D:if(x)
begin ns=B; z=1; end
else D
begin ns=A; z=0; end

endcase
//define state update sequential logic

always @(negedge clr,posedge clk)

if(!clr)
ps<=A;
else
ps<=ns;

endmodule