UNIT-5

Digital System Modeling

1. Data path and control path design

2. GCD system design

3. Traffic light controller design

4. Vending machine design

5. CPU design

Data path and control path design

In a complex digital system,the H/W is typically partioned into two parts

a) Datapath:-which consist of the functional units where all computations are carried out.
typically consist of registers,multiplexers,bus,adder,multipliers,counters and other
functional blocks
b) Control patch:-which implement a FSM and provides control signals to the data path
in a proper sequence.
In responce to the control signals ,various operations are carried out by the data path
Also takes inputs from the data patch regarding various status information

Example:

A=B+C
D=A-C
reg[15:0] A,B,C,D;

B C

D
Example 2: Multiplication by repeated addition
We consider a simple algorithm using repeated start
addition(assume B is non zero)
Read A,B

P=0

P=P+A no
A P B
B=B-1 B=0 yes stop
Comp
Adder

datapath control
path

control path

start s0

A=data_in s1
s0

B=data_in s2
P=0
s1
P=Z
B=B-1
s3
s2

no
Bout=0
s3
yes
done=1 s4
s4
Datapath code:
module mul_datapath(eqz,ldA,ldB,ldP,clrP,decB,dat_in,clk);
input ldA,ldB,ldP,clrP,decB,clk;
input[15:0] data_in;
output eqz;
wire [15:0] x,y,z,bout,bus;
A P B
pipo1 A(x,bus,ldA,clk);
pipo2 P(y,z,ldP,clrP,clk);
cntr B(bout,bus,ldB,decB,clk); Comp
add AD(z,x,y); Adder
comp CMP(eqz,bout);
endmodule

module pipo1 (dout,din,ld,clk)

input [15:0] din;
input ld,clk;
output reg[15:0] dout;
A pipo1 A(x,bus,ldA,clk);
always @(posedge clk)
if(ld)
dout<=din;
endmodule

module pipo2(dout,din,ld,clr,clk);
input [15:0] din;
input ld,clr,clk;
output reg [15:0] dout; P pipo2 P(y,z,ldP,clrP,clk);

always @(posedge clk)

if(clr) dout<=16'b0;
else if(ld) dout<=din;
endmodule

module add(out,in1,in2);
input [15:0] in1,in2;
output reg [15:0] out; Adder add AD(z,x,y);
always @(*)
out=in1+in2;
endmodule

module comp(eqz,data)
input [15:0] data;
output eqz;
comp CMP(eqz,bout);
assign eqz=(data==0);
endmodule B

module cntr(dout,din,ld,dec,clk);
Comp
input [15:0] din;
input ld,dec,clk;
output reg [15:0] dout;
always @(posedge clk)
if(ld) dout<=din; cntr B(bout,bus,ldB,decB,clk);
else if(dec) dout<=dout-1;
endmodule
Control path code:

module controller(ldA,ldB,ldP,clrP,decB,done,clk,eqz,start);
input clk,eqz,start; s0
output reg ldA,ldB,ldP,clrP,decB,done;
reg [2:0] state;
parameter S0=3'b000,s1=3'b001,s2=3'b010,s3=3'b011,s4=3'b100;

always @(posedge clk) s1

begin
case(state) datapath control
path
s0 : if(start) state <=s1;
s2
s1 : state <=s2;
s2 : state <=s3;
s3 : #2 if(eqz) state <=s4;
s4 : state <=s4; s3
default : state <=s0;
endcase
end s4
always @(state)
begin
case(state) start s0
s0 : begin
#1 ldA=0; ldB=0; ldP=0; clrp=0; decB=0;
end A=data_in s1
s1 : begin
#1 ldA=1; B=data_in s2
end P=0
s2 : begin
#1 ldA=0; ldB=1; clrP=1;
end P=Z
s3 : begin B=B-1
s3
#1 ldB=0; ldP=1; clrP=0; decB=1;
end
s4 : begin no
#1 done=1; ldB=0; ldP=0; clrP=0; decB=0; Bout=0
end
default : begin yes
#1 ldA=0; ldB=0; ldP=0; clr=0; decB=0;
done=1 s4
end
endcase
end
endmodule
Testbench:
module mul_test;
reg [15:0] data_in;
reg clk,start;
wire done;
mul_datapath DP(eqz,ldA,ldB,ldP,clrp,decB,data_in,clk);
controller CON(ldA,ldB,ldP,clrP,decB,done,clk,eqz,start);
intial
begin
clk=1'b0;
#3 start=1'b1;
#500 $finish;
end
intial
begin
#17 data_in=17;
#10 data_in=5; output:
end 0 x x
intial 6 x 0
begin 35 0 0
$monitor($time,"%d %b,DP.y,done); 45 17 0
$dumpfile("mul.vcd"); 55 34 0
$dumpvars(0,mul_test); 65 51 0
end 75 68 0
endmodule 85 85 0
88 85 1
Traffic light controller design

consider a controller for traffic at the intersection of a main highway and country road

The following specifications must be considered:

The traffic signal for the main highway gets

highest priority because cars are continuously
main highway
present on the main highway.thus, the main
highway signal remains green by default
Occasionally,cars from the country road arrive
at the traffic signal.the traffic signal for the country country road
road must turn green only long enough to let the
cars on the country road go.
As soon as there are no cars on the country road, the country road traffic signal turns
yellow and then red and the traffic signal on the main highway turns green again.

There is a sensor to detect cars waiting on the country road.the sensor send a signal x
at input to the controller.x=1 if there are cars on the country road,otherwise x=0.
There are delays on transitions from s1 to s2,from s2 to s3,and from s4 to s0.the dealy
must be controllable

x=0
s0
s4 x=1 state signal
s0 hwy=G, cntry=R
s1 hwy=y, cntry=R
x=0 s1 hwy=R, cntry=R
s2
s3 hwy=R, cntry=G
s4 hwy=R, cntry=Y
s3
s2
x=1

verilog code:

'define true 1'b1

'define false 1'b0
'define Y2Rdealy 3 //yellow to red dealy
'define R2Gdealy 2 //red to green dealy

module sig_control(hwy,cntry,x,clock,clear);
output [1:0] hwy,cntry; //2-bit output for 3 states of signals g,y,r
reg [1:0] hwy,cntry;
input x,clock,clear;
parameter red=2'd0, yellow=2'd1, green=2'd2;
parameter s0=3'd0, s1=3'd1, s2=3'd2, s3=3'd3, s4=3'd4;
reg [2:0] state; //internal state variables
reg [2:0] next_state;

//state changes only at positive edge of clock

always @(posedge clock)
if(clear)
state<=s0; //controller starts in s0 state
else
state<=next_state; // state changes

//compute value of main signal and country signal

always @(state)
begin
hwy=green; //default light assignment for highway light
cntry=red; //default light assignment for country light
case(state)
s0: ; //no change ,use deafult
s1: hwy=yellow;
s2: hwy=red;
s3: begin
hwy=red;
cntry=green;
end
s4: begin
hwy=red;
cntry=yellow;
end
endcase
end
//state machine using case statement

always @(state or x)
begin
case(state)
s0 : if(x)
next_state=s1;
else
next_state=s0;
s1 : begin
repeat(y2rdelay) @(posedge clock)
next_state=s2;
end
s2 : begin
repeat(r2gdelay) @(posedge clock)
next_state=s3;
end
s3 : if(x)
next_state=s3;
else
next_state=s4;
s4 : begin
repeat(y2rdealy) @(posedge clock)
next_state=s0;
end
 deafult : next_state=s0;
endcase
end

endmodule

testbench code:

module stimuls;
wire [1:0] main_sig,cntry_sig;
reg car_on_cntry_rd;
reg clock,clear;
//instantiate signal controller

sig_control sc(main_sig, cntry_sig, car_on_cntry_rd, clock, clear);

//set up monitor

intial
$monitor($time,"main sig=%b country sig=%b car_on_cntry_rd=%b",
main_sig, cntry_sig, car_on_cntry_rd);

//set up clock
intial
begin
clock = false;
forever #5 clock=~clock;
end

//control clear signal

intial
begin
clear=true;
repeat (5) @(negedge clock);
clear=false;
end
//apply stimulas
intial
begin
car_on_cntry_rd=false;
repeat(20)@(negedge clock);
car_on_cntry_rd=true;
repeat(10) @(negedge clock);
car_on_cntry_rd=false;
repeat(20)@(negedge clock);
car_on_cntry_rd=true;
repeat(10)@(negedge clock);
$stop;
end
endmodule
 Vending machine design

Ex 1: news paper vending machine

5rs =2'b01
10rs=2'b10
0rs=2'b00
coin machine new_paper

possiblity of receiving coins

clk rst 1.5>5>5=15

2.5>10=15
3.10>5=15
4.10>10=20
s0

s5

s10

s15

verilog code:

module vending_machine(new_paper,coin,clk,rst);
output reg new_paper;
input [1:0] coin;
input clk,rst;
reg[1:0] state;
reg[1:0] next_state;
parameter s0=2'b00, s5=2'b01, s10=2'b10, s15=2'b11;

always @(posedge clk)

begin
if(rst)
state=s0;
else
state=next_state;
end

always@(state,coin)
begin
case(state)
s0 : begin
if(coin==2'b00) next_state=s0;
else if(coin==2'b01) next_state=s5;
else if (coin==2'b10) next_state=s10;
end
s5 : begin
if (coin==2'b00) next_state=s5;
else if(coin==2'b01)next_state=s10; s0
else if(coin==2'b10)next_state=s15;
end
s10:begin
if(coin==2'b00)next_state=s10; s5
else if(coin==2'b01)next_state=s15;
else if(coin==2'b10)next_state=s15;
end
s15:begin s10
next_state=s0;
end
default:next_state=s0;
s15
endcase
end

always@(state)
begin
case(state)
s0:new_paper<=1'b0;
s5:new_paper<=1'b0;
s10:new_paper<=1'b0;
s15:new_paper<=1'b1;
default : new_paper<=1'b0;
endcase
end
endmodule