Serial Adder

Mealy Modelling
PROGRAM
module saddmea (a, b, s,ns, clock, clear);
parameter s0 = 1'b0, s1 = 1'b1;
input a, b, clock, clear;
output s,ns;
reg s;
reg ps, ns;
always @(posedge clock or posedge clear)
begin
if (clear)
begin
ps = s0;
end
else begin
ps = ns;
end
end
always @(ps or a or b) begin
case (ps)
s0: begin
case ({a,b})
2'b00: begin
ns = s0;
s = 0;

end
2'b01: begin
ns = s0;
s = 1;
end
2'b10: begin
ns = s0;
s = 1;
end
2'b11: begin
ns = s1;
s = 0;
end
default: begin
ns = s0;
s = 0;
end
endcase
end
s1: begin
case ({a,b})
2'b00: begin
ns = s0;
s = 1;
end
2'b01: begin

ns = s1;
s = 0;
end
2'b10: begin
ns = s1;
s = 0;
end
2'b11: begin
ns = s1;
s = 1;
end
default: begin
ns = s0;
s = 0;
end
endcase
end
default: begin
ns = s0;
end
endcase
end
endmodule

Test Bench
module mealyfsm_tb;
reg a,b,clock,clear;

wire s,ns;
saddmea m1(a, b, s,ns, clock, clear);
initial
begin
clear=1;clock=0;a=0;b=0;
#100 clear=0;a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=0;
#100 a=1;b=1;
#100 a=0;b=0;
#100 a=0;b=1;
#100 a=1;b=0;
#100 a=1;b=1;
#100 a=0;b=0;
#100 clear=0;
end

Wave Form

Moore Modelling
Program
module saddmoore (a, b, s,ns, clock, clear);

parameter s0 = 2'b00, s1 = 2'b01,s2=2'b10,s3=2'b11;

input a, b, clock, clear;
output s;
output [1:0]ns;
reg s;
reg [1:0]ps,ns;

always @(posedge clock or posedge clear)

begin
if (clear) begin
ps = s0;
s=0;
end
else
begin
ps = ns;
end
end
always @(ps or a or b)
begin
case (ps)
s0: begin
case ({a,b})
2'b00: begin
ns = s0;
s = 0;

end
2'b01: begin
ns = s3;
s = 1;
end
2'b10: begin
ns = s3;
s = 1;
end
2'b11: begin
ns = s1;
s = 0;
end
endcase
end
s1: begin
case ({a,b})
2'b00: begin
ns = s0;
s = 0;
end
2'b01: begin
ns = s1;
s = 0;
end
2'b10: begin

ns = s1;
s = 0;
end
2'b11: begin
ns = s2;
s = 1;
end
endcase
end
s2: begin
case ({a,b})
2'b00: begin
ns = s3;
s = 1;
end
2'b01: begin
ns = s1;
s = 0;
end
2'b10: begin
ns = s1;
s = 0;
end
2'b11: begin
ns = s2;
s = 1;

end
endcase
end
s3: begin
case ({a,b})
2'b00: begin
ns = s0;
s = 0;
end
2'b01: begin
ns = s3;
s = 1;
end
2'b10: begin
ns = s3;
s = 1;
end
2'b11: begin
ns = s1;
s = 0;
end
endcase
end
default: begin
ns = s0;
s=0;

end
endcase
end
endmodule

Test Bench
module moorefsm_tb;
reg a,b,clock,clear;
wire s;
wire[1:0]ns;
saddmoore m1(a, b, s,ns, clock, clear);
initial
begin
clear=1;clock=0;a=0;b=0;
#50 clear=0;a=0;b=0;
#50 a=0;b=1;
#50 a=1;b=0;
#50 a=1;b=1;
#50 a=0;b=0;
#50 a=0;b=1;
#50 a=1;b=0;
#50 a=1;b=1;
#50 a=0;b=0;
#50 a=0;b=1;
#50 a=1;b=0;
#50 a=1;b=1;
#50 a=0;b=0;

#50 a=0;b=1;
#50 a=1;b=0;
#50 a=1;b=1;
clear=1;
end
always
#100 clock=~clock;
endmodule

Waveform

Pattern Detector
Mealy Modelling
Program
module pattmea (a,s,ps, clock, clear);
parameter s1 = 2'b00, s2 = 2'b01, s3 = 2'b10, s4 = 2'b11;
input a,clock, clear;
output s;

output [1:0]ps;
reg s;
reg [1:0]ps,ns;
always @(posedge clock or posedge clear)
begin
if (clear)
begin
ps = s1;
s=0;
end
else begin
ps = ns;
end

end
always @(ps or a) begin
case (ps[1:0])
s1: begin
case (a)
1'b0: begin
ns = s1;
s = 0;
end

1'b1: begin
ns = s2;
s = 0;
end
default: begin
ns = s1;
s = 0;
end
endcase
end
s2: begin
case (a)
1'b0: begin
ns = s3;
assign

s = 0;

end
1'b1: begin
ns = s2;
assign s = 0;
end
default: begin
ns = s1;
assign s = 0;

end
endcase
end
s3: begin
case (a)
1'b0: begin
ns = s4;
s = 0;
end
1'b1: begin
ns = s2;
s = 0;
end
default: begin
ns = s1;
s = 0;
end
endcase
end
s4: begin
case (a)
1'b0: begin
ns = s1;

assign s = 0;
end
1'b1: begin
ns = s2;
ps=s2;
assign s = 1;
end
default: begin
ns = s1;
assign s = 0;
end
endcase
end
default: begin
ns = s1;
end
endcase
end
endmodule
Test Bench
module pattmealyfsm_tb;
reg a,clock,clear;
wire s;

wire [1:0]ps;
pattmea m1(a,s,ps,clock,clear);
initial
begin
clear=0;clock=1;a=0;
#100 a=0;
#100 a=1;
#100 a=0;
#100 a=0;
#100 a=1;
#100 a=0;
#100 a=0;
#100 a=1;
#100 clear=0;
end
always
#50 clock=~clock;
endmodule
Wave Form

Moore Modelling
Program
module pattmoor (a,s,ps, clock, clear);
parameter s1 = 3'b000, s2 = 3'b001, s3 = 3'b010, s4 = 3'b011,s5=3'b100;
input a ,clock, clear;
output s;
output [2:0]ps;
reg s;
reg [2:0]ps,ns;

always @(posedge clock or posedge clear)

begin
if (clear)
begin
ps = s1;
s=0;
end
else begin
ps = ns;
end
end
always @(ps or a) begin
case (ps[2:0])
s1: begin
case (a)
1'b0: begin
ns = s1;
assign s = 0;
end
1'b1: begin
ns = s2;
assign s = 0;
end
default: begin
ns = s1;
assign s = 0;

end
endcase
end
s2: begin
case (a)
1'b0: begin
ns = s3;
assign s = 0;
end
1'b1: begin
ns = s2;
assign s = 0;
end
default: begin
ns = s1;
assign s = 0;
end
endcase
end
s3: begin
case (a)
1'b0: begin
ns = s4;
assign s = 0;
end
1'b1: begin

ns = s2;
assign s = 0;
end
default: begin
ns = s1;
assign s = 0;
end
endcase
end
s4: begin
case (a)
1'b0: begin
ns = s1;
assign s = 0;
end
1'b1: begin
ps = s5;
ns=s5;
assign s = 1;
end
default: begin
ns = s1;
assign s = 0;
end
endcase
end

s5: begin
case (a)
1'b0: begin
ns = s3;
assign s = 0;
end
1'b1: begin
ns = s2;
assign s = 0;
end
default: begin
ns = s1;
assign s = 0;
end
endcase
end
default: begin
ns = s1;
assign s=0;
end
endcase
end
endmodule

Test Bench
module pattmoorefsm_tb;
reg a,clock,clear;

wire s;
wire [2:0]ps;
pattmoor UUT(.a(a),.s(s),.ps(ps),.clock(clock),.clear(clear));
always
#50 clock=~clock;
initial
begin
clear=0;clock=1;a=0;
#100 a=0;
#100 a=1;
#100 a=0;
#100 a=0;
#100 a=1;
#100 a=0;
#100 a=0;
#100 a=1;
#100 clear=0;
end
endmodule

Wave Form