1.design For 4:1 Mux

1.
design for 4:1 mux

module mux4(out,a,b,c,d.s0,s1);
output out;
input a,b,c
module mux_tb();
reg t_a,t_b,t_c,t_d,s0,s1;
wire out;
mux_example mux(s0,s1,a,b,c,d,out);
initial
begin
$monitor("s0=%b,s1=%b,a=%0b,b=%0b,c=%0b,d=%0b-->out=%0b",s0,s1,a,b,c,d,out);
{a,b,c,d}=4'h5;
repeat(6) begin
s0,s1=$randam;
#5;
end
endmodule
module mux_example(
input [1:0] sel,
input i0,i1,i2,i3,
output reg y);
always @(*) begin
case(sel)
2'h0: y = i0;
2'h1: y = i1;
2'h2: y = i2;
2'h3: y = i3;
default: $display("Invalid sel input");
endcase
end
endmodule
test bench for 4:1 mux
module tb;
reg [1:0] sel;
reg i0,i1,i2,i3;
wire y;
mux_example mux(sel, i0, i1, i2, i3, y);
initial begin
$monitor("sel = %b -> i3 = %0b, i2 = %0b ,i1 = %0b, i0 = %0b -> y = %0b", sel,i3,i2,i1,i0, y);
{i3,i2,i1,i0} = 4'h5;
repeat(6) begin
sel = $random;
#5;
end
end
endmodule
Result wave form:

2. 8:1 mux design
entity mux8to1 is
port ( s : in bit_vector (2 downto 0);
d : in bit_vector (7 downto 0);
y : out bit);
end mux8to1;
architecture equation of mux8to1 is
begin
with s select
y <= d(0) when "000",
d(1) when "001",
d(2) when "010",
d(3) when "011",
d(4) when "100",
d(5) when "101",
d(4) when "100",
d(5) when "101",
d(6) when "110",
d(7) when others;
end equation;
Testbench for 8 to 1 Multiplexer
entity testbench is
-- empty
end testbench;
architecture tb of testbench is
-- DUT component
component mux8to1 is
port
( s : in bit_vector (2 downto 0);
d : in bit_vector (7 downto 0);
y : out bit);
end component;
signal s : bit_vector (2 downto 0);
signal d : bit_vector (7 downto 0);
signal y : bit;
begin
-- Connect DUT
DUT: mux8to1 port map(
s => s,
d => d,
y => y );
process
begin
s <= "000";
d <= "00000001";
wait for 1 ns;
s <= "001";
d <= "00000010";
wait for 1 ns;
s <= "010";
d <= "00000100";
wait for 1 ns;
s <= "011";
d <= "00001000";
wait for 1 ns;
s <= "100";
d <= "00010000";
wait for 1 ns;
s <= "101";
d <= "00100000";
wait for 1 ns;
s <= "110";
d <= "01000000";
wait for 1 ns;
s <= "111";
d <= "10000000";
wait for 1 ns;
wait;
end process;
end tb;
result wave form:

3. Design for half adder:
module adder(a,b,sum,cout,result);
input a,b;
output [1:0] sum;
output cout;
output[1:0] result;
assign result=a+b;
assign sum=result[1:0];
assign cout=result[1:0];
endmodule
Test bench for half adder:

module halfadder_tb();
reg t_a,t_b;
wire sum;
wire cout;
adder dut(.a(t_a),.b(t_b),.sum(SUM),.cout(COUT));
initial
begin
$dumpfile("dump.vcd");
$dumpvars(1);
end
initial
begin
t_a=0;
t_b=0;
#5
t_a=1;
t_b=0;
#5
t_a=0;
t_b=1;
#5
$finish();
end
endmodule
Result wave form for half adder:

4. design for one bit full adder:
module Full_Adder (input a, b, c, output cout, sum);
assign #6 sum = (a^b)^c;
assign #7 cout = a&b | (a^b)&c;
endmodule
test bench:
module Test_Full_Adder;
reg a, b, c;
wire sum, cout;
// Instantiate the module to be tested
Full_Adder FA (a, b, c, cout, sum);
initial begin
$dumpfile("Test_Full_Adder.vcd");
$dumpvars(1, FA);
a=0; b=0; c=0;
#20 a=1; b=1;
#20 a=0; b=0; c=1;
#20 a=1; c=0;
#20 $finish;
end
endmodule
Result wave form:

5. 1:4 demultiplexer:
Design:
module Demultiplexer (output reg [3:0] d, input [1:0] s, input a);
always @(d or s or a) begin
case (s)
2'b00 : begin d[0] = a; d[3:1] = 0; end
2'b01 : begin d[1] = a; d[0] = 0; end
2'b10 : begin d[2] = a; d[1:0] = 0; end
2'b11 : begin d[3] = a; d[2:0] = 0; end
endcase
end
endmodule
Test bench:
module Demultiplexer_tb;
wire [3:0] D;
reg [1:0] S;
reg A;
Demultiplexer TB1 (D, S,A);

initial begin
A = 1;
S = 2'b00;
#10 S = 2'b01;
#10 S = 2'b10;
#10 S = 2'b11;
#10 A=0;
S = 2'b00;
#10 S = 2'b01;
#10 S = 2'b10;
#10 S = 2'b11;
End
Result wave form:

6. 1:8 demultiplexer:
Design:
module Demultiplexer(in,s0,s1,s2,d0,d1,d2,d3,d4,d5,d6,d7);
input in,s0,s1,s2;
output d0,d1,d2,d3,d4,d5,d6,d7;
assign d0=(in & ~s2 & ~s1 &~s0),
d1=(in & ~s2 & ~s1 &s0),
d2=(in & ~s2 & s1 &~s0),
d3=(in & ~s2 & s1 &s0),
d4=(in & s2 & ~s1 &~s0),
d5=(in & s2 & ~s1 &s0),
d6=(in & s2 & s1 &~s0),
d7=(in & s2 & s1 &s0);
endmodule
Test bench:
module TestModule;
// Inputs
reg in;
reg s0;
reg s1;
reg s2;
// Outputs
wire d0;
wire d1;
wire d2;
wire d3;
wire d4;
wire d5;
wire d6;
wire d7;
initial
begin
$dumpvars;
end
// Instantiate the Unit Under Test (UUT)
Demultiplexer uut (
.in(in),
.s0(s0),
.s1(s1),
.s2(s2),
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7)
);
initial begin
// Initialize Inputs
in = 0;
s0 = 0;
s1 = 0;
s2 = 0;
// Wait 100 ns for global reset to finish
#100;
in = 1;
s0 = 0;
s1 = 1;
s2 = 0;
#100;
// Add stimulus here
end
end module
Result wave form:
7. 16:1 multiplexer:
Design:
module MULTI(E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10,E11,E12,E13,E14,E15,sel0,sel1,sel2,sel3,S,C1,C2);
input E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10,E11,E12,E13,E14,E15;
input sel0,sel1, sel2, sel3;
output reg S, C1, C2;
always @(E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10,E11,E12,E13,E14,E15,sel0,sel1,sel2,sel3)
begin
case({sel0,sel1,sel2})
3'b000: begin
C1=E8;
C2=E0;
end
3'b001: begin
C1=E9;
C2=E1;
end
3'b010: begin
C1=E10;
C2=E2;
end
3'b011: begin
C1=E11;
C2=E3;
end
3'b100: begin
C1=E12;
C2=E4;
end
3'b101: begin
C1=E13;
C2=E5;
end
3'b110: begin
C1=E14;
C2=E6;
end
3'b111: begin
C1=E15;
C2=E7;
end
endcase
case(sel3)
1'b0: S=C1;
1'b1: S=C2;
endcase
end
endmodule
Test bench:
module test_MULTI();
reg E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10,E11,E12,E13,E14,E15,sel0,sel1,sel2,sel3;
wire S, C1, C2;
MULTI MULTI(E0,E1,E2,E3,E4,E5,E6,E7,E8,E9,E10,E11,E12,E13,E14,E15,sel0,sel1,sel2,sel3,S,C1,C2);
initial
begin
$dumpfile("out.vcd");
$dumpvars(1,test_MULTI);
#10 E0 = 1'b0; sel3 = 1'b1; sel0 = 1'b0; sel1 = 1'b0; sel2 = 1'b0;
#10;
end
initial
#310 $finish;
Endmodule
Result wave form:

8. 2*4 Decoder:
Design:
module decoder2to4(x, enable, y);
input [1:0] x; //this is my decoder input
input enable;
output [3:0] y;
reg [3:0] y;
always @(x, enable ) //
begin
if(enable==0) //if enable isn't on, all outputs WON'T OUTPUT correct and give us 1111
y = 4'b1111;
else //if enable is high...
if (x == 2'b00) //...then we check our inputs and give corresponding outputs
y = 4'b0001;
if (x == 2'b01)
y = 4'b0010;
if (x == 2'b10)
y = 4'b0100;
if (x == 2'b11);
y = 4'b1000;
end
endmodule
Test bench:
module testbench_2to4decoder;
reg [1:0] x; //use reg not wire to assign values
wire [3:0] y; //for the outputs
reg enable;
decoder2to4 uut(x,enable,y);
initial begin
x = 2'b00;
enable = 1'b0; //keep it off
#10 //wait some time
enable = 1'b1; //turn enable on
#10; //wait some time
x = 2'b01; //input 01
#10; //wait some time
x = 2'b10; //input 10
#10; //then
x = 2'b11; //input 11
#10;
enable = 1'b0; //turn it off
#10;
end
initial
begin
$dumpvars(0,testbench_2to4decoder);
$dumpfile("my.vcd");
end
endmodule
Result wave form:

9. 3*8 decoder
Design:
module decoder3to8(
Data_in,
Data_out
);
//what are the input ports and their sizes.
input [2:0] Data_in;
//what are the output ports and their sizes.
output [7:0] Data_out;
//Internal variables
reg [7:0] Data_out;
//Whenever there is a change in the Data_in, execute the always block.
always @(Data_in)
case (Data_in) //case statement. Check all the 8 combinations.
3'b000 : Data_out = 8'b00000001;
3'b001 : Data_out = 8'b00000010;
3'b010 : Data_out = 8'b00000100;

3'b011 : Data_out = 8'b00001000;
3'b100 : Data_out = 8'b00010000;
3'b101 : Data_out = 8'b00100000;
3'b110 : Data_out = 8'b01000000;
3'b111 : Data_out = 8'b10000000;
//To make sure that latches are not created create a default value for output.
default : Data_out = 8'b00000000;
endcase
endmodule
Test bench:
module tb_decoder;
// Declaring Inputs
reg [2:0] Data_in;
// Declaring Outputs
wire [7:0] Data_out;
decoder3to8 uut (
.Data_in(Data_in),
.Data_out(Data_out)
);
initial begin
//Apply Input and wait for 100 ns
Data_in = 3'b000; #100;
Data_in = 3'b001; #100;
Data_in = 3'b010; #100;
Data_in = 3'b011; #100;
Data_in = 3'b100; #100;
Data_in = 3'b101; #100;
Data_in = 3'b110; #100;
Data_in = 3'b111; #100;

end
endmodule
Result wave form:
10. 4*16 Decoder

Design:
module decoder4to16(
Data_in,
Data_out
);
//what are the input ports and their sizes.
input [3:0] Data_in;
//what are the output ports and their sizes.
output [15:0] Data_out;
//Internal variables
reg [15:0] Data_out;
//Whenever there is a change in the Data_in, execute the always block.
always @(Data_in)
case (Data_in) //case statement. Check all the 8 combinations.
4'b0000 : Data_out = 16'b0000000000000001;
4'b0001 : Data_out = 16'b0000000000000010;
4'b0010 : Data_out = 16'b0000000000000100;
4'b0011 : Data_out = 16'b0000000000001000;

4'b0100 : Data_out = 16'b0000000000010000;
4'b0101 : Data_out = 16'b0000000000100000;
4'b0110 : Data_out = 16'b0000000001000000;
4'b0111 : Data_out = 16'b0000000010000000;
//To make sure that latches are not created create a default value for output.
default : Data_out = 16'b0000000000000000;
endcase
endmodule
Test bench:
module tb_decoder;
// Declaring Inputs
reg [3:0] Data_in;
// Declaring Outputs
wire [15:0] Data_out;
decoder4to16 uut (
.Data_in(Data_in),
.Data_out(Data_out)
);
initial
begin
$dumpvars;
end
initial begin
//Apply Input and wait for 100 ns
Data_in = 4'b0000; #100;
Data_in = 4'b0001; #100;
Data_in = 4'b0010; #100;
Data_in = 4'b0011; #100;

Data_in = 4'b0100; #100;
Data_in = 4'b0101; #100;
Data_in = 4'b0110; #100;
Data_in = 4'b0111; #100;
End
Endmodule
Result wave form:
11. 4*2 Encoder:

Design:
module encoder(
input d0,d1,d2,d3,
output a,b);
assign a=d1|d3;
assign b=d2|d3;
endmodule
Test bench:
module encoder42_tb;
reg D0,D1,D2,D3;
wire A,B;
encoder m1(.d0(D0),.d1(D1),.d2(D2),.d3(D3),.a(A),.b(B));
initial
begin
$dumpfile("test.vcd");
$dumpvars;
#10000 $finish;
end
initial begin
D0='b0;
D1='b0;
D2='b0;
D3='b0;
#15 $finish;
end
always #8 D0=~D0;
always #6 D1 = ~D1;
always #4 D2 = ~D2;
always #2 D3=~D3;
always @(A,B)
$display( "time =%0t INPUT VALUES: \t D0=%b D1=%b D2=%b D3=%b \t Outputs:A=%b B=%b ",
$time,D0,D1,D2,D3,A,B);
Endmodule
Result wave form:

12)
Design of 4x2 encoder:
module encoder4_2 ( din ,dout );
output [1:0] dout ;
reg [1:0] dout ;
input [3:0] din ;
wire [3:0] din ;
always @ (din) begin
case (din)
8 : dout = 0;
4 : dout = 1;
2 : dout = 2;
1 : dout = 3;
default : dout = 1'bZ;
endcase
end
endmodule
test bench:
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY tb_encoder IS
END tb_encoder;
ARCHITECTURE behavior OF tb_encoder IS
– Component Declaration for the Unit Under Test (UUT)
COMPONENT encoder
PORT(
a : IN std_logic_vector(3 downto 0);
b : OUT std_logic_vector(1 downto 0)
);
END COMPONENT;
--Inputs
signal a : std_logic_vector(3 downto 0) := (others => '0');
--Outputs
signal b : std_logic_vector(1 downto 0);
BEGIN
– Instantiate the Unit Under Test (UUT)
uut: encoder PORT MAP (
a => a,
b => b
);
Simulation process:
stim_proc: process
begin
– hold reset state for 100 ns.
wait for 100 ns;
a <= "0000";
wait for 100 ns;
a <= "0001";
wait for 100 ns;
a <= "0010";
wait for 100 ns;
a <= "0100";
wait for 100 ns;
a <= "1000";
wait;
end process;
END;
library IEEE;
use IEEE.STD_LOGIC_1164.all;
entity encoder1 is
port(
a : in STD_LOGIC_VECTOR(3 downto 0);
b : out STD_LOGIC_VECTOR(1 downto 0)
);
end encoder1;
architecture bhv of encoder1 is
begin
process(a)
begin
if (a="1000") then
b <= "00";
elsif (a="0100") then
b <= "01";
b <= "10";
b <= "11";
else
b <= "ZZ";
end if;
end process;
end bhv;
wave form:
13)
8x3 encoder with active-low:
Design:
module Encoder(d0,d1,d2,d3,d4,d5,d6,d7,a,b,c);
input d0,d1,d2,d3,d4,d5,d6,d7;
output a,b,c;
or(a,d4,d5,d6,d7);
or(b,d2,d3,d6,d7);
or(c,d1,d3,d5,d7);
endmodule
test bench:
// Inputs
reg d0;
reg d1;
reg d2;
reg d3;
reg d4;
reg d5;
reg d6;
reg d7;
// Outputs
wire a;
wire b;
wire c;
Encoder uut (
.d0(d0),
.d1(d1),
.d2(d2),
.d3(d3),
.d4(d4),
.d5(d5),
.d6(d6),
.d7(d7),
.a(a),
.b(b),
.c(c)
);
initial begin
d0 = 0;
d1 = 0;
d2 = 0;
d3 = 0;
d4 = 0;
d5 = 0;
d6 = 0;
d7 = 0;
#100;
d0 = 0;
d1 = 0;
d2 = 0;
d3 = 1;
d4 = 0;
d5 = 0;
d6 = 0;
d7 = 0;
#100;
end
endmodule
wave form:
13)
8x3 high priorty encoder:
Design:
module prio_enco_8x3(d_out, d_in);
output [2:0] d_out;
input [7:0] d_in ;
assign d_out = (d_in[7] ==1'b1 ) ? 3'b111:
(d_in[6] ==1'b1 ) ? 3'b110:
(d_in[5] ==1'b1 ) ? 3'b101:
(d_in[4] ==1'b1) ? 3'b100:
(d_in[3] ==1'b1) ? 3'b011:
(d_in[2] ==1'b1) ? 3'b010:
(d_in[1] ==1'b1) ? 3'b001:
(d_in[0] ==1'b1) ? 3'b000: 3'bxxx;
end module
Test bench:
module prio_enco_8x3_tst;
reg [7:0] d_in;
wire[2:0] d_out;
prio_enco_8x3 u1 (.d_out(d_out), .d_in(d_in) );
initial
begin
d_in=8'b11001100;
#10;
d_in=8'b01100110;
#10;
d_in=8'b00110011;
#10;
d_in=8'b00010010;
#10;
d_in=8'b00001001;
#10;
d_in=8'b00000100;
#10;
d_in=8'b00000011;
#10;
d_in=8'b00000001;
#10;
d_in=8'b00000000;
# 10;
stop;
end
end module
Wave form:
14)
8x3 low priority encoder:
Design:
module prio_enco_8x3(d_out, d_in);
output [2:0] d_out;
input [7:0] d_in ;
assign d_out = (d_in[7] ==1'b1 ) ? 3'b000:
(d_in[6] ==1'b1 ) ? 3'b001:
(d_in[5] ==1'b1 ) ? 3'b010:
(d_in[4] ==1'b1) ? 3'b011:
(d_in[3] ==1'b1) ? 3'b100:
(d_in[2] ==1'b1) ? 3'b101:
(d_in[1] ==1'b1) ? 3'b110:
(d_in[0] ==1'b1) ? 3'b111: 3'bxxx;
end module
Test bench:
module prio_enco_8x3_tst;
reg [7:0] d_in;
wire[2:0] d_out;
prio_enco_8x3 u1 (.d_out(d_out), .d_in(d_in) );
initial
begin
d_in=8'b00000000;
#10;
d_in=8'b00000001;
#10;
d_in=8'b00000011;
#10;
d_in=8'b00000100;
#10;
d_in=8'b00001001;
#10;
d_in=8'b00010010;
#10;
d_in=8'b00110011;
#10;
d_in=8'b01100110;
#10;
d_in=8'b11001100;
# 10;
stop
end
end module
Wave form:
19)
4 bit magnitude comparartor:
Design:
module comparator(a,b,eq,lt,gt);
input [3:0] a,b;
output reg eq,lt,gt;
always @(a,b)
begin
if (a==b)
begin
eq = 1'b1;
lt = 1'b0;
gt = 1'b0;
end
else if (a>b)
begin
eq = 1'b0;
lt = 1'b0;
gt = 1'b1;
end
else
begin
eq = 1'b0;
lt = 1'b1;
gt = 1'b0;
end
end
endmodule
test bench:
module comparator_tst;
reg [3:0] a,b;
wire eq,lt,gt;
comparator DUT (a,b,eq,lt,gt);
initial
begin
a = 4'b1100;
b = 4'b1100;
#10;
a = 4'b0100;
b = 4'b1100;
#10;
a = 4'b1111;
b = 4'b1100;
#10;
a = 4'b0000;
b = 4'b0000;
#10;
$stop;
end
end module
wave form:
20)
8 bit magnitude comparartor:
Design:
module magComp ( In1,In2,Gt,Lt,Eq);
input [7:0] In1,In2; //The two 8-bit Inputs In1 and In2
output Gt, Lt,Eq;
reg Gt, Lt, Eq;
always @ (In1 or In2)
begin
Gt <= ( In1 > In2 )? 1'b1 : 1'b0;
Lt <= ( In1 < In2 )? 1'b1 : 1'b0;
Eq <= ( In1 == In2)? 1'b1 : 1'b0;
end
endmodule
test bench:
module magComp_tb;
// Inputs
reg [7:0] In1;
reg [7:0] In2;
// Outputs
wire Gt;
wire Lt;
wire Eq;
magComp uut (
.In1(In1),
.In2(In2),
.Gt(Gt),
.Lt(Lt),
.Eq(Eq)
);
initial begin
In1 = 8'b0;
In2 = 8'b0;
#100;
In1 = 8'd8;
In2 = 8'd7;
#20;
In1 = 8'd100;
In2 = 8'd120;
#20;
In1 = 8'd250;
In2 = 8'd250;
#20;
In1 = 8'd0;
In2 = -8'd5;
#20;
In1 = -8'd5;
In2 = -8'd5;
#20;
end
endmodule
wave form:
22)
4 bit adder/subtractor:
Design:
module addsubparameter (A, B, OP, C_out, Sum);
input [1:0] A,B;
input OP;
output[1:0] C_out;
output[1:0] Sum;
wire C_out, Sum;
reg assigning;
always@(OP)
begin
if (OP == 0)
assigning = A + B + OP;
else
assigning = A + (~B + 1) + OP;
end
assign {C_out, Sum} = assigning;
endmodule
module adder (a, b, op, cout, sum);
parameter size = 4 ;
input [3:0] a, b;
output [3:0] sum;
input op;
output cout;
wire [2:0] c;
genvar i;
generate
for (i = 0; i < size; i = i + 1) begin: adder
if (i == 0)
addsubparameter (a[i], b[i], op, sum[i], c[i]);
else if (i == 3)
addsubparameter (a[i], b[i], c[i-1], cout, sum[i]);
else
addsubparameter (a[i], b[i], c[i-1], sum[i], c[i]);
end
endgenerate
endmodule
test bench:
module addsub_tb();
reg [3:0] a;
reg [3:0] b;
reg op;
wire [3:0] sum;
wire cout;
adder DUT (a,b,op,sum,cout);
initial begin
a = 4'b1010; b = 4'b1100; op = 1'b0; #100;
a = 4'b1111; b = 4'b1011; op = 1'b1; #100;
a = 4'b1010; b = 4'b1010; op = 1'b0; #100;
end
endmodule
wave form:
23)
4 bit alu:
Design:
module alu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[8]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule
test bench:
module alu(
input [7:0] A,B, // ALU 8-bit Inputs
input [3:0] ALU_Sel,// ALU Selection
output [7:0] ALU_Out, // ALU 8-bit Output
output CarryOut // Carry Out Flag
);
reg [7:0] ALU_Result;
wire [8:0] tmp;
assign ALU_Out = ALU_Result; // ALU out
assign tmp = {1'b0,A} + {1'b0,B};
assign CarryOut = tmp[8]; // Carryout flag
always @(*)
begin
case(ALU_Sel)
4'b0000: // Addition
ALU_Result = A + B ;
4'b0001: // Subtraction
ALU_Result = A - B ;
4'b0010: // Multiplication
ALU_Result = A * B;
4'b0011: // Division
ALU_Result = A/B;
4'b0100: // Logical shift left
ALU_Result = A<<1;
4'b0101: // Logical shift right
ALU_Result = A>>1;
4'b0110: // Rotate left
ALU_Result = {A[6:0],A[7]};
4'b0111: // Rotate right
ALU_Result = {A[0],A[7:1]};
4'b1000: // Logical and
ALU_Result = A & B;
4'b1001: // Logical or
ALU_Result = A | B;
4'b1010: // Logical xor
ALU_Result = A ^ B;
4'b1011: // Logical nor
ALU_Result = ~(A | B);
4'b1100: // Logical nand
ALU_Result = ~(A & B);
4'b1101: // Logical xnor
ALU_Result = ~(A ^ B);
4'b1110: // Greater comparison
ALU_Result = (A>B)?8'd1:8'd0 ;
4'b1111: // Equal comparison
ALU_Result = (A==B)?8'd1:8'd0 ;
default: ALU_Result = A + B ;
endcase
end
endmodule
wave form:
24)
Positive D-latch:
Design:
module D_pos_lat(
//Assuming by positive you mean positive level of clock
clk,
reset_n,
in,
out );
input clk;
input reset_n;
input in;
output reg out;
always@(*)
begin
if(!reset_n)
out = 1'd0;
else if(clk)
out = in;
end
test bench:
module tb_latch;
// Declare variables that can be used to drive values to the design
reg d;
reg en;
reg rstn;
reg [2:0] delay;
reg [1:0] delay2;
integer i;
// Instantiate design and connect design ports with TB signals
d_latch dl0 ( .d (d),
.en (en),
.rstn (rstn),
.q (q));
// This initial block forms the stimulus to test the design
initial begin
$monitor ("[%0t] en=%0b d=%0b q=%0b", $time, en, d, q);
// 1. Initialize testbench variables
d <= 0;
en <= 0;
rstn <= 0;
// 2. Release reset
#10 rstn <= 1;
// 3. Randomly change d and enable
for (i = 0; i < 5; i=i+1) begin
delay = $random;
delay2 = $random;
#(delay2) en <= ~en;
#(delay) d <= i;
end
End
endmodule
endmodule
results
25)
Negative D-latch:
Design:
module FallingEdge_DFlipFlop_SyncReset(D,clk,sync_reset,Q);
input D; // Data input
input clk; // clock input
input sync_reset; // synchronous reset
output reg Q; // output Q
always @(negedge clk)
begin
if(sync_reset==1'b1)
Q <= 1'b0;
else
Q <= D;
end
endmodule

TEST Bench
module tb_DFF();
reg D;
reg clk;
reg reset;
wire Q;
RisingEdge_DFlipFlop_SyncReset dut(D,clk,reset,Q);
initial begin
clk=0;
forever #10 clk = ~clk;
end
initial begin
reset=1;
D <= 0;
#100;
reset=0;
D <= 1;
#100;
D <= 0;
#100;
D <= 1;
end
endmodule
wave form:
26)
The difference between a D-type latch and a D-type flip-flop is that a latch does not
have a clock signal to change state whereas a flip-flop always does. The D flip-flop is
an edge triggered device which transfers input data to Q on clock rising or falling edge.
27)
Positive edge trigger:
Design:
module dff (input d,
input rstn,
input clk,
output reg q);
always @ (posedge clk)
if (!rstn)
q <= 0;
else
q <= d;
endmodule
test bench:
module tb_dff;
reg clk;
reg d;
reg rstn;
reg [2:0] delay;
dff dff0 ( .d(d),
.rsnt (rstn),
.clk (clk),
.q (q));
// Generate clock
always #10 clk = ~clk;
// Testcase
initial begin
clk <= 0;
d <= 0;
rstn <= 0;
#15 d <= 1;
#10 rstn <= 1;
for (int i = 0; i < 5; i=i+1) begin
delay = $random;
#(delay) d <= i;
end
end
endmodule
wave form:
28)
Negative edge trigger:
module dff (output reg op, input ip, input clk, input rst);
always @(negedge clk or posedge rst) begin
if (rst) op <= 1′b0;
else
op <= ip;
end
endmodule
29)
2 bit up binary counter:
module counter_2bit ( clk ,reset ,dout );
output [1:0] dout ;
reg [1:0] dout ;
input clk ;
wire clk ;
input reset ;
wire reset ;
initial dout = 0;
always @ (posedge (clk)) begin
if (reset)
dout <= 0;
else
dout <= dout + 1;
end
endmodule
test bench:
module DFF( input d, input en, output q, output qb );
assign a = ( en & ( ~ d ));
assign b = ( en & d );
assign q = ~ ( a | qb );
assign qb = ~ ( b | q );
endmodule //Testbench initial begin
// Initialize
Inputs d = 0; en = 0;
// Wait 100 ns for global reset to finish #100;
// Add stimulus here #100;
d = 0;
en = 1; #100;
d = 1;
en = 0; #100;
d = 1;en = 1;
end
wave form:
30) and 31)
Structural:
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity updown_count is
Port ( clk,rst,updown : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end updown_count;
architectural behaviour:
signal temp:std_logic_vector(3 downto 0):="0000";
begin
process(clk,rst)
begin
if(rst='1')then
temp<="0000";
elsif(rising_edge(clk))then
if(updown='0')then
temp<=temp+1;
else
temp<=temp-1;
end if;
end if;
end process;
count<=temp;
end Behavioral;
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity sync_counter_tb is
end entity;
architecture tb of sync_counter_tb is
component updown_count is
Port ( clk,rst,updown : in STD_LOGIC;
count : out STD_LOGIC_VECTOR (3 downto 0));
end component;
signal clk, rst, updown : STD_LOGIC := '0';
signal count : STD_LOGIC_VECTOR (3 downto 0);
constant num_of_clocks : integer := 20;
signal i : integer := 0;
constant T : time := 20 ns;
begin
uut: updown_count port map(
clk => clk,
rst => rst,
updown => updown,
count => count);
process
begin
rst <= '0';
clk <= '0';
wait for T/2;
clk <= '1';
wait for T/2;
if (i = num_of_clocks) then
wait;
else
i <= i + 1;
end if;
if (i < 10) then
updown <= '0';
else
updown <= '1';
end if;
end process;
end tb;
wave form:
32)
4 bit up down cunter:
module sync_up_down_load_counter(clk,load,rst,ctrl,din,count);
parameter N=4;
input clk,rst,load,ctrl;
input [N-1:0]din;
output reg [N-1:0]count;
always@(posedge clk)
begin
if(rst)
count<=0;
else if (load)
count<=din;
else
begin
case(ctrl)
1'b0:count<=count+1;
1'b1:count<=count-1;
endcase
end
end
endmodule
test bench:
module sync_up_down_load_counter_tb();
reg rst,clk,load,ctrl;
reg [3:0]din;
wire [3:0]count;
sync_up_down_load_counter SA(clk,load,rst,ctrl,din,count);
initial
begin
clk=0;
forever #5 clk=~clk;
end
task initiaize();
begin
#5;
rst=0;
clk=0;
load=0;
din=0;
end
endtask
task reset();
begin
@(negedge clk)
rst=1'b1;
@(negedge clk)
rst=1'b00;
end
endtask
task data(input [3:0]a);
begin
@(negedge clk)
load=1;
din=a;
@(negedge clk)
load=0;
end
endtask
task control(c);
begin
@(negedge clk)
ctrl=c;
end
endtask
initial
begin
initiaize;
reset;
control(0);
repeat(17)
@(negedge clk)
#5;
data(4'd18);
repeat(17)
@(negedge clk)
#5;
data(4'd5);
control(1);
repeat(17)
@(negedge clk);
#5;
data(4'd17);
repeat(17)
@(negedge clk)
#5;
data(4'd5);
end
initial
$monitor("Input rst=%b,clk=%b,din=%b,load=%b Output count=%b",rst,clk,din,load,count);
initial
#1500 $finish;
Endmodule
Wave form:
33)
Design:
module jLFSR(Q, clock, reset);
output reg [3:0] Q;
input clock, reset;
always @(posedge clock)
begin
if(reset)
Q <= 4'b1111;
else
Q <= { Q[2:0], (Q[3] ^ Q[0]) };
end
endmodule
Verilog code:
module jLFSRTb;
wire [3:0] Q;
reg clock, reset;
jLFSR jlfsr(Q, clock, reset);
initial
begin
clock =0;
reset = 1; #10; reset = 0; #10;
#200;
$finish;
end
always #5 clock = ~clock;
//enabling the wave dump
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
endmodule
wave form:
34) and 35)

4 bit bi directional shift register:
module biShiftReg74194(D, S, SDR, SDL, CLRb, CLK, Q);
input[3:0] D;
input[1:0] S;
input SDR, SDL, CLRb, CLK;
output reg [3:0] Q;
initial begin
Q <= 0;
end
always @(CLK, CLRb)
begin
if(CLRb == 0)
Q <= 4'b0000;
else if(CLK == 1)
begin
case(S)
0: Q <= Q;
1: Q <= {Q[2:0],SDL};
2: Q <= {SDR, Q[3:1]};
3: Q <= D;
endcase
end
end
endmodule
wave form:
36)
4 bit ring counter:
Design:
module ring_counter(
Clock,
Reset,
Count_out
);
input Clock;
input Reset;
output [3:0] Count_out;
reg [3:0] Count_temp;
always @(posedge(Clock),Reset)
begin
if(Reset == 1'b1) begin
Count_temp = 4'b0001; end
else if(Clock == 1'b1) begin
Count_temp = {Count_temp[2:0],Count_temp[3]}; end
end
assign Count_out = Count_temp;
endmodule
test bench:
module tb_ring;
reg Clock;
reg Reset;
wire [3:0] Count_out;
ring_counter uut (
.Clock(Clock),
.Reset(Reset),
.Count_out(Count_out)
);
initial Clock = 0;
always #10 Clock = ~Clock;
initial begin
Reset = 1;
#50;
Reset = 0;
end
endmodule
wave form:
37)
8 bit ring counter:
Design:
module ring_ctr #(parameter WIDTH=8)
(
input clk,
input rstn,
output reg [WIDTH-1:0] out
);
always @ (posedge clk) begin

if (!rstn)
out <= 1;
else begin
out[WIDTH-1] <= out[0];
for (int i = 0; i < WIDTH-1; i=i+1) begin
out[i] <= out[i+1];
end
end
end
endmodule
test bench:
module tb;
parameter WIDTH = 8;
reg clk;
reg rstn;
wire [WIDTH-1:0] out;
ring_ctr u0 (.clk (clk),
.rstn (rstn),
.out (out));
initial begin
{clk, rstn} <= 0;
$monitor ("T=%0t out=%b", $time, out);
repeat (2) @(posedge clk);
rstn <= 1;
$finish;
end
initial begin
$dumpvars;
end
endmodule
wave form:
38)
4 bit johnson counter:
Design:
module johnson_ctr #(parameter WIDTH=4)
(
input clk,
input rstn,
);
if (!rstn)
out <= 1;
else begin
out[WIDTH-1] <= ~out[0];
out[i] <= out[i+1];
end
end
end
endmodule
test bench:
module tb;
reg clk;
reg rstn;
johnson_ctr u0 (.clk (clk),
.rstn (rstn),
.out (out));
initial begin
{clk, rstn} <= 0;
rstn <= 1;
$finish;
end
initial begin
$dumpvars;
end
endmodule
wave form:
39)
8 bit johnson counter:
Design:
module johnson_ctr #(parameter WIDTH=8)
(
input clk,
input rstn,
);
if (!rstn)
out <= 1;
else begin
out[WIDTH-1] <= ~out[0];
out[i] <= out[i+1];
end
end
end
endmodule
test bench:
module tb;
reg clk;
reg rstn;
johnson_ctr u0 (.clk (clk),
.rstn (rstn),
.out (out));
initial begin
{clk, rstn} <= 0;
rstn <= 1;
$finish;
end
initial begin
$dumpvars;
end
endmodule
wave form:
40)
8x8 single port memory:
Design:
module ram_single #(
parameter DATA_WIDTH=8, //width of data bus
parameter ADDR_WIDTH=8 //width of addresses buses
)(
input [(DATA_WIDTH-1):0] data, //data to be written
input [(ADDR_WIDTH-1):0] addr, //address for write/read operation
input we, //write enable signal
input clk, //clock signal
output [(DATA_WIDTH-1):0] q //read data
);
reg [DATA_WIDTH-1:0] ram [2**ADDR_WIDTH-1:0];
reg [ADDR_WIDTH-1:0] addr_r;
always @(posedge clk) begin //WRITE
if (we) begin
ram[addr] <= data;
end
addr_r <= addr;
end
assign q = ram[addr_r]; //READ
endmodule
41)
Design:
module fifo #(
parameter WIDTH = 4,
parameter DEPTH = 4
)(
input [WIDTH-1:0] data_in,
input wire clk,
input wire write,
input wire read,
output reg [WIDTH-1:0] data_out,
output wire fifo_full,
output wire fifo_empty,
output wire fifo_not_empty,
output wire fifo_not_full
);
// memory will contain the FIFO data.
reg [WIDTH-1:0] memory [0:DEPTH-1];
// $clog2(DEPTH+1)-2 to count from 0 to DEPTH
reg [$clog2(DEPTH)-1:0] write_ptr;
reg [$clog2(DEPTH)-1:0] read_ptr;
// Initialization
initial begin
// Init both write_cnt and read_cnt to 0
write_ptr = 0;
read_ptr = 0;
// Display error if WIDTH is 0 or less.
if ( WIDTH <= 0 ) begin
$error("%m ** Illegal condition **, you used %d WIDTH", WIDTH);
end
// Display error if DEPTH is 0 or less.
if ( DEPTH <= 0) begin
$error("%m ** Illegal condition **, you used %d DEPTH", DEPTH);
end
end // end initial
assign fifo_empty = ( write_ptr == read_ptr ) ? 1'b1 : 1'b0;
assign fifo_full = ( write_ptr == (DEPTH-1) ) ? 1'b1 : 1'b0;
assign fifo_not_empty = ~fifo_empty;
assign fifo_not_full = ~fifo_full;
if ( write ) begin
memory[write_ptr] <= data_in;
end
if ( read ) begin
data_out <= memory[read_ptr];
end
end
always @ ( posedge clk ) begin
if ( write ) begin
write_ptr <= write_ptr + 1;
end
if ( read && fifo_not_empty ) begin
read_ptr <= read_ptr + 1;
end
end
endmodule
wave form:
42)
Design:
// This is linear queue / FIFO
// The queue length 8
// The data width is also 8 bits
module jFIFO(DATAOUT, full, empty, clock, reset, wn, rn, DATAIN);
output reg [7:0] DATAOUT;
output full, empty;
input [7:0] DATAIN;
input clock, reset, wn, rn; // Need to understand what is wn and rn are for
reg [2:0] wptr, rptr; // pointers tracking the stack
reg [7:0] memory [7:0]; // the stack is 8 bit wide and 8 locations in size
assign full = ( (wptr == 3'b111) & (rptr == 3'b000) ? 1 : 0 );
assign empty = (wptr == rptr) ? 1 : 0;
always @(posedge clock)
begin
if (reset)
begin
memory[0] <= 0; memory[1] <= 0; memory[2] <= 0; memory[3] <= 0;
memory[4] <= 0; memory[5] <= 0; memory[6] <= 0; memory[7] <= 0;
DATAOUT <= 0; wptr <= 0; rptr <= 0;
end
else if (wn & !full)
begin
memory[wptr] <= DATAIN;
wptr <= wptr + 1;
end
else if (rn & !empty)
begin
DATAOUT <= memory[rptr];
rptr <= rptr + 1;
end
end
endmodule
test bench:
module jFIFOTb;
wire [7:0] DATAOUT;
wire full, empty;
reg clock, reset, wn, rn;
reg [7:0] DATAIN;
jFIFO jfifo(DATAOUT, full, empty, clock, reset, wn, rn, DATAIN);
//enabling the wave dump
initial begin
$dumpfile("dump.vcd"); $dumpvars;
end
initial
begin
clock = 0; DATAIN = 8'd0;
reset = 1; clock = 1; #5 ; clock = 0; #5;
reset = 0;
$display("Start testing");
// First write some data into the queue
wn = 1; rn = 0;
DATAIN = 8'd100;
clock = 1; #5 ; clock = 0; #5;
DATAIN = 8'd150;
clock = 1; #5 ; clock = 0; #5;
DATAIN = 8'd200;
clock = 1; #5 ; clock = 0; #5;
DATAIN = 8'd40;
clock = 1; #5 ; clock = 0; #5;
DATAIN = 8'd70;
clock = 1; #5 ; clock = 0; #5;
DATAIN = 8'd65;
clock = 1; #5 ; clock = 0; #5;
DATAIN = 8'd15;
clock = 1; #5 ; clock = 0; #5;
// Now start reading and checking the values
wn = 0; rn = 1;
clock = 1; #5 ; clock = 0; #5;
if ( DATAOUT === 8'd100 )
$display("PASS %p ", DATAOUT);
else
$display("FAIL %p ", DATAOUT);
clock = 1; #5 ; clock = 0; #5;
else
clock = 1; #5 ; clock = 0; #5;
else
clock = 1; #5 ; clock = 0; #5;
else
clock = 1; #5 ; clock = 0; #5;
else
clock = 1; #5 ; clock = 0; #5;
else
clock = 1; #5 ; clock = 0; #5;
else
clock = 1; #5 ; clock = 0; #5;
if ( empty === 1 )
$display("PASS %p ", empty);
else
$display("FAIL %p ", empty);
end
endmodule
wave form:
43)
module arbiter_k (req0,req1,req2,req3,gnt0,gnt1,gnt2,gnt3,rst,clk);
input wire req0,req1,req2,req3,rst,clk;
output reg gnt0,gnt1,gnt2,gnt3;
reg [2:0] state;
reg [2:0] nxt_state;
//defining types of states required
parameter [2:0] IDLE=000,
REQ0=001,
REQ1=010,
REQ2=011,
REQ3=100;
always@(posedge clk) //for transition of states
begin
if(rst)
state <=IDLE;
else
state <= nxt_state;
end
always@(state,req0,req1,req2,req3) // conditions for states
begin
case(state)
IDLE:begin
case({req0,req1,req2,req3})
4'b0000:nxt_state=IDLE;
4'b0001:nxt_state=REQ3;
endcase
end
REQ0: begin
if(req0&&((req1||~req1)||(req2||~req2)||(req3||~req3)))
begin
gnt0=1;
gnt1=0;
gnt2=0;
gnt3=0;
$display($time,"req0 is granted");
nxt_state=REQ1;
end
else
nxt_state= REQ0;
end
REQ1:begin
begin
gnt0=0;
gnt1=1;
gnt2=0;
gnt3=0;
nxt_state=REQ2;
end
else
nxt_state= REQ1;
end
REQ2: begin
begin
gnt0=0;
gnt1=0;
gnt2=1;
gnt3=0;
nxt_state=REQ3;
end
else
nxt_state= REQ2;
end
REQ3:begin
begin
gnt0=0;
gnt1=0;
gnt2=0;
gnt3=1;
nxt_state=REQ0;
end
else
nxt_state= REQ3;
end
default:
$display($time,"invalid request");
endcase
end
endmodule
test bench
module test_k();
reg req0,req1,req2,req3,rst,clk;
wire gnt0,gnt1,gnt2,gnt3;
arbiter_k n1(.req0(req0),.req1(req1),.req2(req2),.req3(req3),
.gnt0(gnt0),.gnt1(gnt1),.gnt2(gnt2),.gnt3(gnt3),.rst(rst),.clk(clk));
always //generating clock pulses
#2 clk=~clk;
initial
begin
clk=0;
rst=0;
#2 rst=1;
#2 rst=0;
#500 $finish;
end
always@(posedge clk) //stimulus generation
if(rst)
begin
req0 <= 1'b0;
req1 <= 1'b0;
req2 <= 1'b0;
req3 <= 1'b0;
end
else
begin
req0 <= $random;
req1 <= $random;
req2 <= $random;
req3 <= $random;
end
endmodule
waveform
44)
Gray codes have the property that only one bit
changes between successive elements in the sequence.
In a binary code, you could have an arbitrarily large
number of bits change between two successive numbers.
Gray Code is a form of binary that uses a different method
of incrementing from one number to the next. With Gray
Code, only one bit changes state from one position to another.
This feature allows a system designer to perform some
error checking (i.e., if more than one bit changes,
the data must be incorrect
decimal binary graycode
0 000 000
1 001 001
2 010 011
3 011 010
4 100 110
5 101 111
6 110 101
7 111 100
45)
finally, one-hot encoding consists in using one bit

representing each state, so that at any point in time, a
state will be encoded as a 1 in the bit that represents the
current state, and 0 in all other bits. This may not seem
very efficient at first because of the number of bits used,
and the excessive number of invalid states. However, one-hot encoding is
very good at simplifying the stimulus logic for the flip flops
because there’s no need to decode the states.
The bits are the states.
0000001 --1st stage
0000010---2nd stage
0000100---3rd stage
0001000---4th stage
0010000---5th stage
0100000---6th stage
1000000---7th stage
46) & 47)
One hot encoding is encoding of a finite state machine where
each state will take a separate flip flop. If u hav 8 states
in Finite state machine then encoder requires 8 flip flops.
Same state machine requires only three ff'f in Gray and Binary encoding.
One hot encoding will increase the speed but area utilisation will
be more.
Binary encoding is a binary count of the state machine number in sequence

and implement very less logic.
Binary encoding is the simplest state machine encoding and
all possible states are defined and there is no possibility
of a hang state.
states binary one hot
s1 000 001
s2 001 010
s3 010 100
48)
In binary encoding we need 3 bits to get 8 states
49)
In one hot encoding we need 8 bits to get 8 states

50)
To represent eight states, we need at least three bits.

1.design For 4:1 Mux

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1.design For 4:1 Mux

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1.

design for 4:1 mux

input [1:0] sel,

output reg y);

always @(*) begin

default: $display("Invalid sel input");

reg [1:0] sel;

mux_example mux(sel, i0, i1, i2, i3, y);

Result wave form:

port ( s : in bit_vector (2 downto 0);

d : in bit_vector (7 downto 0);

architecture equation of mux8to1 is

y <= d(0) when "000",

d(1) when "001",

d(2) when "010",

d(3) when "011",

d(4) when "100",

d(5) when "101",

d(4) when "100",

d(5) when "101",

d(6) when "110",

d(7) when others;

Testbench for 8 to 1 Multiplexer

( s : in bit_vector (2 downto 0);

d : in bit_vector (7 downto 0);

signal s : bit_vector (2 downto 0);

signal d : bit_vector (7 downto 0);

DUT: mux8to1 port map(

wait for 1 ns;

wait for 1 ns;

wait for 1 ns;

wait for 1 ns;

wait for 1 ns;

wait for 1 ns;

wait for 1 ns;

wait for 1 ns;

result wave form:

output [1:0] sum;

Test bench for half adder:

Result wave form for half adder:

module Full_Adder (input a, b, c, output cout, sum);

assign #6 sum = (a^b)^c;

assign #7 cout = a&b | (a^b)&c;

wire sum, cout;

// Instantiate the module to be tested

Full_Adder FA (a, b, c, cout, sum);

a=0; b=0; c=0;

#20 a=1; b=1;

#20 a=0; b=0; c=1;

#20 a=1; c=0;

Result wave form:

always @(d or s or a) begin

2'b00 : begin d[0] = a; d[3:1] = 0; end

2'b01 : begin d[1] = a; d[0] = 0; end

2'b10 : begin d[2] = a; d[1:0] = 0; end

2'b11 : begin d[3] = a; d[2:0] = 0; end

Demultiplexer TB1 (D, S,A);

Result wave form:

assign d0=(in & ~s2 & ~s1 &~s0),

d1=(in & ~s2 & ~s1 &s0),

d2=(in & ~s2 & s1 &~s0),

d3=(in & ~s2 & s1 &s0),

d4=(in & s2 & ~s1 &~s0),