2:1 Multiplexer Logic Diagram

Select/Switc Out
h
0 I0

1 I1

Y = I0.S’ + I1.S
Verilog Code
If else Statement Case Statement Testbench
module m2to1b( i0, i1, s, y); module m2to1b(y,i0,i1,s); module mux2to1_tb;
input i0; wire y;
input wire i0, i1, s; input i1;
reg i0,i1,s;
output reg y; mux2to1b
input s; m1(.y(y),.i0(i0),.i1(i1),.s(s));
always @(s) output y; initial
begin reg y; begin
if(s) always @ (s) i0=1'b0; i1=1'b0; s=1'b0;
case (s) #10 i0=1'b1; i1=1'b0; s=1'b0;
y= i1; 0: y = i0; #10 i0=1'b0; i1=1'b1; s=1'b1;
else 1: y = i1; #10 i0=1'b1; i1=1'b0; s=1'b1;
end
y=i0; default: y = 1'bx;
endmodule
end endcase
endmodule endmodule
Verilog Code

Gate Level Data Flow Behavioral

module mux2to1(y,i0,i1,s); module m2to1d(i0, i1, s,
output y; module m2to1d(i0, i1, s, y); y);
input i0,i1,s; output y; output y;
wire w1,w2,sbar; input i0, i1, s; input i0, i1, s;
and a1(w1,i0,sbar); assign y= (~s&i0)|(s&i1); reg y;
not n1(sbar,s); endmodule always @(s)
and a2(w2,s,i1); y= (~s&i0)|(s&i1);
or o1(y,w1,w2); endmodule
endmodule
1 to 4 Demultiplexer
Verilog Code
Behavioral
module demux1to4(y,a,din); Dataflow
output reg [3:0] y; module demux1to4d(y,a,din);
input [1:0] a;
output [3:0] y;
input din;
input [1:0] a;
always @(a,din)
input din;
begin
case (a) assign y[0] = din & (~a[0]) & (~a[1]);
2'b00 : begin y[0] = din; y[3:1] = 0; end assign y[1] = din & (~a[1]) & a[0];
2'b01 : begin y[1] = din; y[0] = 0; end assign y[2] = din & a[1] & (~a[0]);
2'b10 : begin y[2] = din; y[1:0] = 0; end assign y[3] = din & a[1] & a[0];
2'b11 : begin y[3] = din; y[2:0] = 0; end endmodule
endcase
end
endmodule
4 to 2 Encoder
Verilog Code
module encod4to2b(dout,din);
module encod4to2(d0,d1,d2,d3,q0,q1); input [3:0]din;
output [1:0]dout ;
output q0,q1; reg [1:0]dout;
input d0,d1,d2,d3; always @ (din)
case (din)
assign q0 = d1 | d3; 4'b0001 : dout = 2'b00;
assign q1 = d3 | d2; 4'b0010 : dout = 2'b01;
4'b0100 : dout = 2'b10;
endmodule 4'b1000 : dout = 2'b11;
default : dout = 2'bxx;
endcase
endmodule
2 to 4 Decoder
Verilog Code Decoder
Behavioral Level Data Flow
module decoder2to4(en,a,b,y);
module decoder24_data(en,a,b,y);
input en,a,b;
output reg [3:0]y; input en,a,b;
always @(en,a,b) output [3:0]y;
Begin wire enb,na,nb;
if(en==0) assign enb = ~en;
begin assign na = ~a;
if(a==1'b0 & b==1'b0) y=4'b1110; assign nb = ~b;
else if(a==1'b0 & b==1'b1) y=4'b1101; assign y[0] = ~(enb&na&nb);
else if(a==1'b1 & b==1'b0) y=4'b1011;
assign y[1] = ~(enb&na&b);
else if(a==1 & b==1) y=4'b0111;
else y=4'bxxxx; assign y[2] = ~(enb&a&nb);
end assign y[3] = ~(enb&a&b);
else
y=4'b1111; endmodule
end
endmodule