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module priorityencoder4to2 (input wire [3:0] w, output wire o1, o2, v);
wire c1, nc2;
or G1(o1, w[3], w[2]);
not G2(nc2, w[2]);
and G3(c1, w[1], nc2);
or G4 (o2, w[3], c1);
or G5 (v, w[3], w[2], w[1], w[0]);
endmodule
2)
module priorityencoder4to2 (input wire [3:0]w , output reg o1,o2,v);
always@ (*) begin
if(w[3] == 1'b1)
begin
o1 = 1'b1;
o2 = 1'b1;
v = 1'b1;
end
else if(w[2] == 1'b1)
begin
o1 = 1'b1;
o2 = 1'b0;
v = 1'b1;
end
else if(w[1] == 1'b1)
begin
o1 = 1'b0;
o2 = 1'b1;
v = 1'b1;
end
else if (w[0] == 1'b1)
begin
o1 = 1'b0;
o2 = 1'b0;
v = 1'b1;
end
else
begin
o1 = 1'b0;
o2 = 1'b0;
v = 1'b0;
end
end
endmodule
3)
module priorityencoder4to2_TB();
reg [3:0] TB_w;
wire TB_o1, TB_o2, TB_v;
priorityencoder4to2 UUT(TB_w, TB_o1, TB_o2, TB_v);
initial begin
TB_w[3] = 0;
TB_w[2] = 1;
TB_w[1] = 1;
TB_w[0] = 1;
#10;
$display("Input: w = %b %b %b %b, Output: o1 = %b, o2 = %b, v = %b", TB_w[3],
TB_w[2], TB_w[1], TB_w[0], TB_o1, TB_o2, TB_v);
$finish;
end
endmodule
Module FourBitFullAdder (input wire [3:0] w1, w2, input subtract, output [3:0]
Result, output Cout);
Reg [3:0] temp;
wire c1, c2, c3, c4;
FullAdder F1(w1[0],w2[0],subtract, subtract, temp[0],c1);
FullAdder F2(w1[1], w2[1],c1,subtract, temp[1],c2);
FullAdder F3(w1[2],w2[2],c2,subtract, temp[2],c3);
FullAdder F4(w1[3],w2[3],c3,subtract, temp[3],c4)
assign Result = temp;
assign Cout = c4;
endmodule
4) HDL dataflow description of a fourbit adder-subtractor of
unsigned numbers.
module FourBitAdderSubtractor (input wire A, input wire B, input wire subtract,
output wire result);
assign result = subtract? (A - B) : (A + B);
endmodule