1

BASIC GATES

input a,b;

output AND,OR,NOT,XOR,XNOR;

assign AND=a &b;

assign OR=a | b;

assign NOT=~a;

assign XOR=a^b;

assign XNOR=~(a^b);

endmodule

TEST BENCH

module gate_tb;

reg a1,b1;

wire y1,y2,y3,y4,y5;

gate gate_tb(.a(a1),.b(b1),.AND(y1),.OR(y2),.NOT(y3), .XOR(y4),.XNOR(y5));

initial begin

// $monitor(a1,b1,y1);

$dumpfile("dump.vcd");

$dumpvars(1);

a1=1'b0;

b1=1'b0;

#1 $display("a1:%b,b1:%b,y1:%b,y2:%b,y3:%b,y4:%b,y5:%b", a1,b1,y1,y2,y3,y4,y5);

a1=1'b0;

b1=1'b1;
#1 $display("a1:%b,b1:%b,y1:%b,y2:%b,y3:%b,y4:%b,y5:%b", a1,b1,y1,y2,y3,y4,y5);

a1=1'b1;

b1=1'b0;

#1 $display("a1:%b,b1:%b,y1:%b,y2:%b,y3:%b,y4:%b,y5:%b", a1,b1,y1,y2,y3,y4,y5);

a1=1'b1;

b1=1'b1;

#1 $display("a1:%b,b1:%b,y1:%b,y2:%b,y3:%b,y4:%b,y5:%b", a1,b1,y1,y2,y3,y4,y5);
2

end

endmodule

OUTPUT

HALF ADDER

TEST BENCH

module HA_tb;

reg a1,b1;

wire y1,y2;

HA HA_tb(.a(a1),.b(b1),.sum(y1),.carry(y2));

initial begin

// $monitor(a1,b1,y1);

$dumpfile("dump.vcd");

$dumpvars(1);

a1=1'b0;

b1=1'b0;

#1 $display("a1:%b,b1:%b,y1:%b, y2:%b ",a1,b1,y1,y2);

a1=1'b0;

b1=1'b1;

#1 $display("a1:%b,b1:%b,y1:%b, y2:%b ",a1,b1,y1,y2);

a1=1'b1;

b1=1'b0;

#1 $display("a1:%b,b1:%b,y1:%b, y2:%b ",a1,b1,y1,y2);

a1=1'b1;

b1=1'b1;

#1 $display("a1:%b,b1:%b,y1:%b, y2:%b ",a1,b1,y1,y2);

3

end

endmodule

STRUCTURAL OR GATE LEVEL

module HA(a,b,sum,carry);
input a,b;

output sum,carry;

xor(sum,a,b);

and(carry,a,b);

endmodule

DATA FLOW LEVEL

module HA(a,b,sum,carry);

input a,b;

output sum,carry;

assign sum=a ^b;

assign carry=a&b;

endmodule

BEHAVIORAL LEVEL

module HA(a,b,sum,carry);

input a,b;

output reg sum,carry;

always@(a,b)

begin
sum=a^b;

carry=a&b;
end
endmodule
4

FULL ADDER

module FA(a,b,cin,sum,cout);

input a,b,cin;

output sum,cout;
wire sum1,carry1;

wire sum2,carry2;

HA ha1(a,b,sum1,carry1);

HA ha2(sum1,cin,sum2,carry2);

assign sum=sum2;

assign cout=carry1|carry2;

endmodule

module HA(a,b,sum,carry);

input a,b;

output sum,carry;

assign sum=a^b;

assign carry=a &b;

endmodule

TEST BENCH

module FA_tb;

reg a1,b1,c1;

wire y1,y2;

FA gate_tb(.a(a1),.b(b1),.cin(c1),.sum(y1),.cout(y2));

initial begin

$dumpfile("dump.vcd");
$dumpvars(1);

a1=1'b0;

b1=1'b0;

c1=1'b0;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

a1=1'b0;

b1=1'b0;
5

c1=1'b1;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

a1=1'b0;
b1=1'b1;

c1=1'b0;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

a1=1'b0;

b1=1'b1;

c1=1'b1;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

a1=1'b1;

b1=1'b0;

c1=1'b0;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

a1=1'b1;

b1=1'b0;

c1=1'b1;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

a1=1'b1;

b1=1'b1;

c1=1'b0;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

a1=1'b1;

b1=1'b1;

c1=1'b1;

#1 $display("a1:%b,b1:%b,c1:%b, y1:%b , y2:%b",a1,b1,c1,y1,y2);

end

endmodule
6

BINARY TO GRAY CODE CONVERTER

module bintogray(b2,b1,b0,g2,g1,g0);
input b2,b1,b0;

output g2,g1,g0;

assign g2=b2;

assign g1=b2 ^ b1;

assign g0=b1 ^ b0;

endmodule
TEST BENCH

module tbbintogray;

wire g2,g1,g0;

reg b2,b1,b0;

bintogray m1(.g2(g2),.g1(g1),.g0(g0),.b2(b2),.b1(b1),.b0(b0));

initial
begin

$monitor("\t%b\t%b\t%b\t%b\t%b\t%b",b2,b1,b0,g2,g1,g0);

$dumpfile("test.vcd");

$dumpvars();
7

{b2,b1,b0}=3'b000;

#2

{b2,b1,b0}=3'b001;
#2

{b2,b1,b0}=3'b010;

#2

{b2,b1,b0}=3'b011;

#2

{b2,b1,b0}=3'b100;

#2

{b2,b1,b0}=3'b101;

#2

{b2,b1,b0}=3'b110;

#2

{b2,b1,b0}=3'b111;

end

endmodule

GRAY TO BINARY CODE CONVERTER

module graytobin(g2,g1,g0,b2,b1,b0);

output b2,b1,b0;
input g2,g1,g0;

assign b2=g2;

assign b1=g2 ^ g1;

assign b0=g2 ^g1 ^ g0;

endmodule
8

TEST BENCH

module tbgraytobin;

wire b2,b1,b0;
reg g2,g1,g0;

graytobin m1(.b2(b2),.b1(b1),.b0(b0),.g2(g2),.g1(g1),.g0(g0));

initial

begin

$monitor("\t%b\t%b\t%b\t%b\t%b\t%b",g2,g1,g0,b2,b1,b0);

$dumpfile("test.vcd");

$dumpvars();

{g2,g1,g0}=3'b000;

#2

{g2,g1,g0}=3'b001;

#2

{g2,g1,g0}=3'b010;

#2

{g2,g1,g0}=3'b011;

#2

{g2,g1,g0}=3'b100;
#2

{g2,g1,g0}=3'b101;

#2

{g2,g1,g0}=3'b110;

#2

{g2,g1,g0}=3'b111;

end
9

endmodule

OUTPUT

MUX

module mux4to1(y,i0,i1,i2,i3,s1,s0);

output y;

input i0,i1,i2,i3;

input s1,s0;

assign y=(~s1 & ~s0 & i0)|(~s1 & s0 & i1)|(s1 & ~s0 & i2)|(s1 & s0 & i3);

endmodule

TEST BENCH

module tbmux4to1;

wire y;
reg s1,s0,i0,i1,i2,i3;

mux4to1 m1(.y(y),.i0(i0),.i1(i1),.i2(i2),.i3(i3),.s1(s1),.s0(s0));

initial

begin

$monitor("\t%b\t%b\t%b\t%b\t%b\t%b\t%b",s1,s0,i0,i1,i2,i3,y);

$dumpfile("test.vcd");

$dumpvars();

i0=1'b1;i1=1'b1;i2=1'b1;i3=1'b1;

{s1,s0}=2'b00;
10

#2

{s1,s0}=2'b01;

#2

{s1,s0}=2'b10;
#2

{s1,s0}=2'b11;

end

endmodule

OUTPUT

DEMUX

module dmux4to1(i0,i1,i2,i3,s1,s0,d);

output i0,i1,i2,i3;

input s1,s0,d;
assign i0=~s1 & ~s0 & d;

assign i1=~s1 & s0 & d;

assign i2=s1 & ~s0 & d;

assign i3=s1 & s0 & d;

endmodule

TEST BENCH

module tbdmux4to1;

wire i0,i1,i2,i3;

reg s1,s0,d;

dmux4to1 m1(.i0(i0),.i1(i1),.i2(i2),.i3(i3),.s1(s1),.s0(s0), .d(d));

11

initial

begin

$monitor("\t%b\t%b\t%b\t%b\t%b\t%b\t%b",s1,s0,d,i0,i1,i2,i3);

$dumpfile("test.vcd");

$dumpvars();

d=1'b1;

{s1,s0}=2'b00;

#2

{s1,s0}=2'b01;

#2

{s1,s0}=2'b10;

#2

{s1,s0}=2'b11;

end

endmodule