/*OR GATE*/ module orgate(a,b,c,); input a,b,; output c; reg c; always@(a or b) case(a) 1'b0:c=b; 1'b1:c=1; endcase endmodule OUTPUT

FOR OR GATE:

/*AND GATE*/ module andgate(a,b,c); input a,b; output c; reg c; always@(a or b) case(a) 1'b0:c=0; 1'b1:c=b; endcase endmodule OUTPUT FOR AND GATE:

/*NOR GATE*/ module norgate(a,b,c); input a,b; output c; reg c; always@(a or b) case(a) 1'b0:c=~b; 1'b1:c=0; endcase endmodule OUTPUT FOR NOR GATE:

/*NAND GATE*/ module nandgate(a,b,c); input a,b; output c; reg c; always@(a or b) case(a) 1'b0:c=1; 1'b1:c=~b; endcase endmodule OUTPUT FOR NAND GATE:

/*XOR GATE*/ module exorgate(a,b,c); input a,b; output c; reg c; always@(a or b) case(a) 1'b0:c=b; 1'b1:c=~b; endcase endmodule OUTPUT FOR XOR GATE:

/*NOT GATE*/ module notgate(a,b); input a; output b; reg b; always@(a) case(a) 1'b0:b=1; 1'b1:b=0; endcase endmodule OUTPUT FOR NOT GATE:

/* XNOR GATE*/ module xnorgate(a,b,c); input a,b; output c; reg c; always@(a or b) case(a) 1'b0:c=~b; 1'b1:c=b; endcase endmodule OUTPUT FOR XNOR GATE: