homework 5

1)

2)
module pro(
   input reset,
   input clk,
   input [7:0] N,
   output outy
   );
   wire [5:0] w;
   wire h,i,j;
   data D1(reset,clk,N,w,h,i,j,outy);
   control C1(reset,clk,h,i,j,w);
endmodule

module data(
   input reset,
   input clk,
    input [7:0] in_n,
   input [5:0] words,
   output n_no,
   output n0_1,
   output c_5,
   output out
   );
   wire [7:0] a,b,c;
   wire [3:0] d,e,f;
   wire g;
   mux #(8)m1(in_n,a,words[0],b);
   register_8 r1(reset,clk,b,words[2],c);
   shift s1(c,a);
   mux #(4)m2(0,d,words[1],e);
   register_4 r2(reset,clk,e,words[3],f);
   add a1(f,d);
   mux #(1) m3(1,0,words[4],g);
   ts t1(g,words[5],out);
   assign n_no=(c!=0);
   assign n0_1=(c[0]==1);
   assign c_5=(f==5);
endmodule

module control(
   input reset,
   input clk,
   input n_no,
   input n0_1,
   input c_5,
   output reg[5:0] words
   );
   reg [2:0] state,next_state;
   always@(posedge clk or posedge reset)
   begin
   if(reset) state<=0;
   else state<=next_state;
   end
   always@(*)
   begin
   case(state)
   3'b000:next_state=3'b001;
   3'b001:if(n_no&&n0_1) next_state=3'b010;
          else if(n_no&&n0_1==0) next_state=3'b011;
          else if(n_no==0&&c_5==0) next_state=3'b100;
          else if(n_no==0&&c_5) next_state=3'b101;
  3'b010:next_state=3'b011;
  3'b011:next_state=3'b001;
  3'b100:next_state=3'b100;
  3'b101:next_state=3'b101;
  endcase
  end
  always@(*)
  begin
  case(state)
  3'b000:words=6'b001111;
  3'b001:words=6'b000000;
   3'b010:words=6'b001000;
  3'b011:words=6'b000100;
  3'b100:words=6'b100000;
  3'b101:words=6'b110000;
  endcase
  end
endmodule

3)
与lab6重复。

4)
加-减法器略：

module CU( inputclk,

        inputzis0,
        inputz2is0,
        outputregAloadZ,
        outputregAloadX,
        outputregAloadY,
        outputregAloadW,
        outputreg[2:0]f,
        outputregAOS
);
reg[2:0]state;
parameterS_000=3'b000;
parameterS_001=3'b001;
parameterS_010=3'b010;
 parameterS_011=3'b011;
parameterS_100=3'b100;
parameterS_101=3'b101;
   
always@(posedgeclk)begin
case(state)
   S_000:state<=S_001;
   S_001:begin
   if(zis0)state<=S_000; elseif(~zis0)state<=S_010; end
S_010:begin if(z2is0)state<=S_011; elseif(~z2is0)state<=S_100; end
S_011:state<=S_101; S_100:state<=S_101; S_101:state<=S_000;
default:state<=S_000;
endcase end
   
always@(*)begin
   case(state)
S_000:begin
AloadZ =1;
AloadX =0; AloadY =0; AloadW =0;
end
S_001:begin
   AloadZ =0; AloadX =0; AloadY =0; AloadW =0;
end
S_010:begin AloadZ =0; AloadX =0; AloadY =0; AloadW =1; f=3'b011; AOS =0;
end
S_011:begin AloadZ =0; AloadX =0; AloadY =1; AloadW =0; f=3'b110;
AOS =1;
end
S_100:begin
   AloadZ =0; AloadX =1; AloadY =0; AloadW =0; f=3'b101; AOS =1;
end
S_101:begin
   AloadZ =1; AloadX =0; AloadY =0; AloadW =0; f=3'b000; AOS =0;
end
default:begin AloadZ =0; AloadX =0; AloadY =0; AloadW =0; f=3'b000; AOS =0;
end
endcase end
endmodule

module DP( inputclk,

         inputAloadZ,
         inputAloadY,
         inputAloadX,
         inputAloadW,
         input[3:0]f,
         inputAOS,
         outputregzis0,
         outputregz2is0 );
   
reg[3:0]x,y,z,w; initialw=3'b000; initialx=3'b000; initialy=3'b000;
initialz=3'b000;
reg[3:0]newx,newy,newz,neww;
   
always@(posedgeclk)begin
   if(AloadZ)z<=newz;
   if(AloadX)x<=newx;
if(AloadY)y<=newy;
 if(AloadW)w<=neww;
end
   
always@(*)begin
   if(z==0)zis0 =1;
   else if(z!=0)zis0 =0;
   if(z%2==0)z2is0 =1;
   else if(z%2!=0)z2is0 = 0;
   if(f==3'b011&&AOS==0)neww=w-1;
   else if(f==3'b101&&AOS==1)newx=x+2;
   else if(f==3'b110&&AOS==1)newy=y+1;
   else if(f==3'b000&&AOS==0)newz=z-1;
end

endmodule

module top( input clk );

wire zis0;
   wire z2is0;
   wire AloadZ;
   wire AloadX;
   wire AloadY;
   wire AloadW;
wire[2:0]f;
wire AOS;
   
   CU
CU1(.clk(clk),.zis0(zis0),.z2is0(z2is0),.AloadZ(AloadZ),.ALoadX(ALoadX),.AloadY(
ALoadY),.ALo     adW(AloadW),.f(f),.AOS(AOS));
DP
DP1(.clk(clk),.zis0(zis0),.z2is0(z2is0),.AloadZ(AloadZ),.ALoadX(ALoadX),.AloadY(
ALoadY),.ALoad W(AloadW),.f(f),.AOS(AOS));
endmodule