VERILOG CODE MUX8 VERILOG CODE

module mux8(y,d,c); module barrel_shifter(d,q,s);

input[7:0]d; input [7:0] d;

output y; input [2:0] s;

reg y; output [7:0] q;

input [2:0]c; mux8 m1(q[7],{d[0],d[7:1]},s);

always @ (c) mux8 m2(q[6],{d[1:0],d[7:2]},s);

begin mux8 m3(q[5],{d[2:0],d[7:3]},s);

if (c==3'b000) mux8 m4(q[4],{d[3:0],d[7:4]},s);

y = d[0]; mux8 m5(q[3],{d[4:0],d[7:5]},s);

else if (c==3'b001) mux8 m6(q[2],{d[5:0],d[7:6]},s);

y = d[1]; mux8 m7(q[1],{d[6:0],d[7]},s);

else if (c==3'b010) mux8 m8(q[0],d[7:0],s);

y = d[2]; endmodule

else if (c==3'b011)

y = d[3]; TEST BENCH

else if (c==3'b100) initial begin
y = d[4]; // Initialize Inputs
else if (c==3'b101) d = 8'b00000001;
y = d[5]; s = 3'b000;
else if (c==3'b110) #100;
y = d[6]; s = 3'b001;
else if (c==3'b111) #100;
y = d[7]; s = 3'b010;
end #100;
endmodule s = 3'b011;

#100;

s = 3'b100;

#100;