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    SAMET KEMAL ÖZDEMİR
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    The document provides a state diagram and Verilog code for a finite state machine (FSM) with 4 states (s1, s2, s3, s4). It includes an example Verilog module that implements the FSM with always blocks to handle registering the current state, determining the next state, and producing the output. The module takes in a clock, reset and input and produces an output and the current state.

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    The document provides a state diagram and Verilog code for a finite state machine (FSM) with 4 states (s1, s2, s3, s4). It includes an example Verilog module that implements the FSM with always blocks to handle registering the current state, determining the next state, and producing the output. The module takes in a clock, reset and input and produces an output and the current state.

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    6 views2 pages

    LAB2

    Uploaded by

    SAMET KEMAL ÖZDEMİR
    The document provides a state diagram and Verilog code for a finite state machine (FSM) with 4 states (s1, s2, s3, s4). It includes an example Verilog module that implements the FSM with always blocks to handle registering the current state, determining the next state, and producing the output. The module takes in a clock, reset and input and produces an output and the current state.

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    © All Rights Reserved
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    of 2

    CME4456 Reconfigurable Computing – Lab 2

    For the following state diagram, write Verilog code and test it with using a waveform.

    case(CS)
    s1:if(in) Y=1'b0;else Y=1'b0;
    s2:if(in) Y=1'b0;else Y=1'b1;
    s3:if(in) Y=1'b0;else Y=1'b1;
    s4:if(in) Y=1'b0;else Y=1'b1;
    default:Y=1'b0;
    endcase

    EXAMPLE:

    module fsm(clk,reset,in,out,Y);
    input clk,reset,in;
    output Y,out;
    reg[1:0] out,CS,NS;
    reg Y;
    parameter s1=2'b00, s2=2'b01,s3=2'b10,s4=2'b11;
    always @(posedge clk or posedge reset)
    begin:Register
    if(reset)CS=s1;else CS=NS;
    end
    always@(in or CS)
    begin:Transitions
    case(CS)
    s1:if(in)NS=s1;else NS=s2;
    s2:if(in)NS=s1;else NS=s3;
    s3:if(in)NS=s4;else NS=s3;
    s4:if(in)NS=s1;else NS=s2;
    default:NS=s1;
    endcase

    end
    always@(in or CS)
    begin:Output
    case(CS)
    s1:if(in) Y=1'b0;else Y=1'b0;
    s2:if(in) Y=1'b0;else Y=1'b1;
    s3:if(in) Y=1'b0;else Y=1'b1;
    s4:if(in) Y=1'b0;else Y=1'b1;
    default:Y=1'b0;
    endcase
    out= CS;
    end
    endmodule

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