PONDICHERRY ENGINEERING COLLEGE

DEPARTMENT OF ELECTRONICS AND COMMUNICATIOM ENG.,

VLSI SIMULATION ASSIGNMENT

NAME : AKASH.S
REGISTER NUMBER : 18EC1005
YEAR : 3 RD YEAR
CLASS AND SEC : ECE-‘A’

AKASH.S
18EC1005
QUESTION:
6. Two four-bit signed numbers, X = x3x2x1x0 and Y = y3y2y1y0, can be compared by using the
subtractor circuit which performs the operation X − Y . The three outputs denote the following:

Z = 1 if the result is 0; otherwise Z = 0

N = 1 if the result is negative; otherwise N = 0

V = 1 if arithmetic overflow occurs; otherwise V = 0

Show how Z, N, and V can be used to determine the cases X = Y , X < Y, X ≤ Y , X > Y, and X ≥ Y.

Solution:
Consider first the case X < Y , where the following possibilities may arise:

If X and Y have the same sign there will be no overflow, hence V = 0. Then for both positive and
negative X and Y the difference will be negative (N = 1).

If X is negative and Y is positive, the difference will be negative (N = 1) if there is no overflow (V = 0);
but the result will be positive (N = 0) if there is overflow (V = 1).

Therefore, if XY if Z + (N ⊕ V ) = 1 and X ≥ Y if N ⊕ V = 1.

The case X = Y is detected by Z = 1. Then, X ≤ Y is detected by Z + (N ⊕ V ) = 1. The last two cases are just
simple inverses: X>Y if Z + (N ⊕ V ) = 1 and X ≥ Y if N ⊕ V = 1

Circuit Diagram:

AKASH.S
18EC1005
PROGRAM:
module assignment(

input [3:0] x,

input [3:0] y,

output reg [2:0] a,

input reset, clk

);

wire c1,s1,c2,s2,c3,s3,c4,s4,z1,z2,z3,n,v,b1,b2;

fulladder o1(x[0],y[0],1,s1,c1);

fulladder o2(x[1],y[1],c1,s2,c2);

fulladder o3(x[2],y[2],c2,s3,c3);

fulladder o4(x[3],y[3],c3,n,c4);

nor(z1,s1,s2);

nor(z2,z1,s3);

nor(z,z2,n);
xor(v,s3,n);

xor(b1,n,v);

or(b2,z,b1);

// we are having 5 cases for testing to represent each case we are using a binary value for each case.

// 000 for x=y

// 001 for x<y

// 010 for x<=y

// 011 for x>y

// 100 for x>=y

AKASH.S
18EC1005
always@(posedge clk,posedge reset)

begin

if(reset)

a=3'b000;

else

begin

if(z==0)

begin

a=3'b000;

end

if(x[3]==1)

begin

if(b1==1)

a=3'b001;

else if(b2==1)

a=3'b010;

end

if(y[3]==1)

begin

if(b1==1)

a=3'b100;

else if(b2==1)

a=3'b011;

end

end

end

endmodule

AKASH.S
18EC1005
TEST FIXTURE:

initial begin

// Initialize Inputs

reset=1'b1;

clk=1'b0;

#10 reset=1'b0;

x = 4'b1010;

y = 4'b0100;

#100 $finish;

end

always

begin

#5 clk = ~clk;

end

endmodule

AKASH.S
18EC1005
OUTPUT:

RESULT:
Thus the given program is executed and the output is verified.

AKASH.S
18EC1005