C:\Xilinx\bin\BE_B_2014\FSM_1101.

vhd
1 library IEEE;
2 use IEEE.STD_LOGIC_1164.ALL;
3 use IEEE.STD_LOGIC_ARITH.ALL;
4 use IEEE.STD_LOGIC_UNSIGNED.ALL;
5
6 entity FSM_1101 is
7 Port ( clk,rst : in std_logic;
8 x : in std_logic;
9 y : out std_logic);
10 end FSM_1101;
11
12 architecture Behavioral of FSM_1101 is
13 type STATE_TYPE is (S0, S1, S2, S3);
14 attribute ENUM_ENCOinputG: STRING;
15 -- attribute ENUM_ENCOinputG of STATE_TYPE: type is "0001 0001 0010 1000";
16 -- signal CS, NS: STATE_TYPE;
17 begin
18 ---------------------------------------------------------------------------------------
19 SYNC_PROC: process(CLK,RST)
20 begin
21 if rst = '1' then
22 CS <= s0;
23 y <= '0';
24 elsif (clk'event and clk = '1') then
25 CS <= NS;
26
27 end if;
28 end process;
29 ------------------------------------------------------------------------------------
30 COMB : process (CS, NS,X )
31 begin
32
33 case CS is
34 when S0 =>
35 if X = '1' then
36 NS <= S1;
37 y <= '0';
38 else
39 NS <= S0;
40 y <= '0';
41 end if;
42 -----------------------------
43 when S1 =>
44 if X = '1' then
45 NS <= S2;
46 y <= '0';
47 else
48 NS <= S0;
49 y <= '0';
50 end if;
51 ----------------------
52 when S2 =>
53 if X = '1' then
54 NS <= S2;
55 y <= '0';
56 else
57 NS <= S3;
58 y <= '0';
59 end if;
60 ------------------------
61 when S3 =>
62 if X = '1' then
63 NS <= S1;
64 y <= '1';
65
66 else
67 NS <= S0;
68 y <= '0';
69 end if;
70 ---------------------
71 WHEN OTHERS =>
72 NULL;
73
74 end case;
75 end process;
76
77 end Behavioral;
C:\Xilinx\bin\BE_B_2014\FSM_1101_bugfree.vhd
1 -- Desined By : Prof Shailendra Badwaik
2 library IEEE;
3 use IEEE.STD_LOGIC_1164.ALL;
4 use IEEE.STD_LOGIC_ARITH.ALL;
5 use IEEE.STD_LOGIC_UNSIGNED.ALL;
6
7 entity FSM_1101_bugfree is
8 Port ( clk,rst : in std_logic;
9 x : in std_logic;
10 y : out std_logic);
11 end FSM_1101_bugfree;
12
13 architecture Behavioral of FSM_1101_bugfree is
14 type STATE_TYPE is (S0, S1, S2, S3);
15 attribute ENUM_ENCOinputG: STRING;
16 attribute ENUM_ENCOinputG of STATE_TYPE: type is "0001 0001 0010 1000";
17 signal CS, NS: STATE_TYPE;
18 signal y_s : std_logic;
19 begin
20 ---------------------------------------------------------------------------------------
21 SYNC_PROC: process(CLK,RST)
22 begin
23 if rst = '1' then
24 CS <= s0;
25 y <= '0';
26 elsif (clk'event and clk = '1') then
27 CS <= NS;
28 y <= y_s;
29 end if;
30 end process;
31 ------------------------------------------------------------------------------------
32 COMB : process (CS, NS,X )
33 begin
34
35 case CS is
36 when S0 =>
37 if X = '1' then
38 NS <= S1;
39 y_s <= '0';
40 else
41 NS <= S0;
42 y_s <= '0';
43 end if;
44 -----------------------------
45 when S1 =>
46 if X = '1' then
47 NS <= S2;
48 y_s <= '0';
49 else
50 NS <= S0;
51 y_s <= '0';
52 end if;
53 ----------------------
54 when S2 =>
55 if X = '1' then
56 NS <= S2;
57 y_s <= '0';
58 else
59 NS <= S3;
60 y_s <= '0';
61 end if;
62 ------------------------
63 when S3 =>
64 if X = '1' then
65 NS <= S1;
66 y_s <= '1';
67
68 else
69 NS <= S0;
70 y_s <= '0';
71 end if;
72 ---------------------
73 WHEN OTHERS =>
74 NULL;
75
76 end case;
77 end process;
78
79 end Behavioral;
80