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Curso:
Diseño Digital I
Practica_18
Docente:
Dr. Jesús Roberto Millán Almaraz
Alumnos:
Cortez Peñuelas Luis Fernando
López Soto Jesús Alberto
3er año
June 8, 2022
Active-HDL Student Edition
1 fsm_contador_m4.vhd
library ieee;
use ieee.std_logic_1164.all;
entity fsm_contador_m4 is
port(
RST,CLK : in std_logic;
opc : in std_logic;
Q : out std_logic_vector(1 downto 0)
);
end fsm_contador_m4;
c1 : process(qp,opc)
begin
case(qp) is
--s0
when "00" =>
Q <= "00";
if(opc='0') then
qn <= "01";
else
qn <= "11";
end if;
--s1
when "01" =>
Q <= "01";
if(opc='0') then
qn <= "10";
else
qn <= "00";
end if;
--s2
when "10" =>
Q <= "10";
if(opc='0') then
qn <= "11";
else
qn <= "01";
end if;
--s3
when others =>
Q <= "11";
if(opc='0') then
qn <= "00";
else
qn <= "10";
end if;
end case;
1
Active-HDL Student Edition
Active-HDL Student Edition
end process;
secuencial : process(RST,CLK)
begin
if(RST='0') then
qp <= (others => '0');
elsif(CLK'event and CLK='1') then
qp <= qn;
end if;
end process;
end fsm;
2
Active-HDL Student Edition
C:/My_Designs/fsm_contador_m4/fsm_contador_m4/fsm_contador_m4/src/wavevhdl.asdb untitled.awc
Signal name Value 240 320 400 480 560 640 720 800 ns
qp 0 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1
qn 1 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0
RST 0
CLK 0
opc 0
Q 0 2 3 0 1 2 3 0 1 2 3 0 1 2 3 0 1 2 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1
Cursor 1
1/2 ( 152 956 ps - 872 754 ps )
C:/My_Designs/fsm_contador_m4/fsm_contador_m4/fsm_contador_m4/src/wavevhdl.asdb untitled.awc
Signal name Value 960 1040 1120 1200 1280 1360 1440 1520 ns
qp 0 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3
qn 1 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2
RST 0
CLK 0
opc 0
Q 0 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3 2 1 0 3
Cursor 1
2/2 ( 872 754 ps - 1 592 552 ps )