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An FSM is a state register and two functions
Output output
Next Logic o
next state
State D Q
input s s
Logic
i
clk
State
Register
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A Simple Counter
Suppose you want to build an FSM with the following state diagram
rst count
n
3
r' r' r' r'
0 1 2 3 31
r r r r
module Counter1(clk,rst,out) ;
input rst, clk ; // reset and clock
output [4:0] out ;
State Next State reg [4:0] next ;
~rst rst DFF #(5) count(clk, next, out) ;
0 1 0
1 2 0 always@(rst, out) begin
casex({rst,out})
2 3 0 6'b1xxxxx: next = 0 ;
. 6'd0: next = 1 ;
6'd1: next = 2 ;
. 6'd2: next = 3 ;
. 6'd3: next = 4 ;
6'd4: next = 5 ;
6'd5: next = 6 ;
30 31 0 6'd6: next = 7 ;
31 0 0 …
6'd30: next = 31 ;
6'd31: next = 0 ;
default: next = 0 ;
endcase
end
endmodule
Datapath Implementation
6
Make Table Symbolic
30 31 0
31 0 0
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Alternate description (symbolic table)
module Counter1(clk,rst,out) ; module Counter1(clk,rst,out) ;
input rst, clk ; // reset and clock input rst, clk ; // reset and clock
output [4:0] out ; output [4:0] out ;
reg [4:0] next ; reg [4:0] next ;
DFF #(5) count(clk, next, out) ; DFF #(5) count(clk, next, out) ;
A simple counter
next_state = rst ? 0 : state + 1
0
1
n next count
Mux2 D Q
n n
+1 0
n
clk
rst
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Sequential Datapath
Output output
Next Logic o
next state
State D Q
input s s
Logic
i
clk
State
Register
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Datapath Sequential Logic
- UDL counter and timer
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An Up/Down/Load (UDL) Counter
30 0 31 29 in
31 0 0 30 in
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Symbolic Table version
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Schematic of UDL Counter
3
n
in next count
2 D Q
n Mux4 n n
^
+/-1 1
n
0
0 clk
n
4
rst
up
down C
L
load
module UDL_Count1(clk, rst, up, down, load, in, out) ;
parameter n = 4 ;
input clk, rst, up, down, load ;
input [n-1:0] in ;
output [n-1:0] out ;
wire [n-1:0] out ;
reg [n-1:0] next ;
Mux3
-1 2
n
in next count done
1 D Q =0
n n n
0
0
n
rst clk
load Select
Logic
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module Timer(clk, rst, load, in, done) ;
parameter n=4 ;
input clk, rst, load ;
input [n-1:0] in ;
output done ;
reg [n-1:0] next_count ;
wire [n-1:0] count ;
Write a Verilog module for an arbitrary-width counter that after being reset,
increment by 3 each clock if an inc input is asserted, decrement by 3 if a
dec input is asserted, and hold its value otherwise.
module IncDecBy3(clk, rst, inc, dec, out) ;
...
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Datapath Sequential Logic - Shift register
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Shift Register
0
1
n next state
Mux2 D Q
n n
sin shl 0
n
clk
rst
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module Shift_Register1(clk, rst, sin, out) ;
parameter n = 4 ;
input clk, rst, sin ;
output [n-1:0] out ;
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Left/Right/Load Shift Register
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module LRL_Shift_Register1(clk, rst, left, right, load, sin, in, out) ;
parameter n = 4 ;
input clk, rst, left, right, load, sin ;
input [n-1:0] in ;
output [n-1:0] out ;
reg [n-1:0] next ;
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