20E138L

Logic Design

Experiment 8

SEGMENT DISPLAY AND OCTAL TOBINARY PRIORITY

BCD TO 7 ENCODER

Aim:
segment display
To rig up a circuit to decode BCD to 7
binary
Torig up a circuit to encode octal to

Components Required: IC 74148,7447,7404

Theory:
Brief note from prescribed text book

BCDto seven segment display

Circuit diagram:

Pin no. 3
or 8
RaI

7447 4702

Vee

Truth table for lamp test

LT RBI BI/RBO BCD input Display modes

Lamp
X
0 X Test
0 X
Display
X X Blink
Any valid Normal
1 BCD no decoding
Nonnally at logicl o/p Any valid Zero
goes to logic 0during BCD no blinking
zero blinking interval

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Dept. of E&I., S.J.C.E., JSS S&TU,Mysuru
 20EI38L
Logic Design

Procedure:

For BCD to 7 segment

perform the following tests
.Rig up the circuit as shown in figure &
one to BI/RBO & observe theseven segments of
Apply logic zero level to LT & logic
the LED must be ON
segments go off.
LT & logic zero to BI/RBO and observe the seven
Apply logic one to
numbers displayed on the
one to BURBO Observe the
Apply logic one to LT & logic
0000-1000
LED for different input from

Truth Table

C .d .e f 7seg O/p
B A .a
D C
1 1
0 () 0 (0
1
1
0 3
1 4
0
0

1 1 6
1 0 7
1 1
0

Octal to binary Encoder

Circuit diagram:

Carry Output

74148 A; Binary Output

Vcc|

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 Truth table

Input Output
3 4 5 6 7 C B A GS EO
EI 0
X X X X X X 1 1
X X
0 1 1 1 1
0 1 1 0
X
X X 0 0
0
X X X 0
X X X 0
0 X X X X X
X X X X X X 0 1
X X X X X X
1 1 1 1 1
0 1 1 1 1

Procedure:

Check allthe components for their working

Insert appropriate IC into the IC base
Make connection as shown in the circuit diagram
Verify the truth table and observe the output

Result:

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Dept. of E&I., S.J.C.E., JSS S&TU,Mysuru
 Experiment 9
FLIPFLOPS

Aim: To rig up and to check the working ofRS flip flop, T flip flops, D flip flops, JK flip-flop,
Master slave flip flop using NANDgates.
Components: IC7404, IC 7410, IC7400, 1C Trainer kit.

Theory:
Brief note from the prescribed textbook.

i. RS Flip Flop

Truth Table

U1
R
R Invalid
1 0
1
1 No change
U2

Truth Table
ii. Clocked RS Flip-Flop

U3 SN7400 S R CIk Qn+1 Qn+1

. 3N7400
(0 Qn Qn

1 0
CK U2SN740 Invalid

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Logic Design
20EI38L
i. DElip Flop
Truth Table

U1 U2

D CIk

U3 Qo
U5 0

iv. T Flip-Flop
Truth Table
UT U3
T, CIk nt1
0
Qn
-]

U5 U4

V. JK Flip-Flop Truth Table

K CIk Qnt1
U1 U3 Qn+1
0 0 Qn Qn
1 0
U2 U4
1

Dept. of E&I., S.J.C.E., JSS S&TU,Mysuru 31

 20EI38L
Logic Design

vi. Master Slave Flip-Flop

U3

TruthTable

J K CIk@n+1 nt1

1
1 0

Procedure:
the figure.
1. Rig up the RS latch as shown in
and verify the truth table.
2. Clock the circuit using a mono pulse
shown in the fig.
3. Rig up the JK flip flop circuit as
table. For J = K = 1, observe the
4. Clock the circuit using a mono pulse and verify the truth
toggling state with race around condition.
5. Similarly verify thetruth table for D andT flipflop.
6. Rig up the master slave circuit as shown in the fig.
7. Connect the monopulse and verify the truth trble, and observe the elimination of race
around condition.

Result:

Dept.of E&I, S.J.C.E., JSS S&TU,Mysuru 32

Logic Design 20EI38L
Experiment10
SHIFT REGISTER

Aim:
PISO, PIPO operation using IC7495
To study the shift left, shift right, SIP0, SISO,
(4 bit shift register).
To study the operation of Ring and Johnson counters.

Components: IC 7495
Circuit Diagram:
SN74LS95
13
6 MODE
12
9 cLK1 QB
8 HCLK2 QC 11
SER
2 A
3
4

HD 14 7

Vcc GND

Truth table for SISO

INPUTS
OUTPUTS
M Clocks Parallel
Serial
CIkl CIk2 A B D QA QB Qc QD
0 X X X X X X X X
X b X X X X X X X
X X X X X X
X d X X X X X X X
X X X X X X X X X
X X X X X X X X X C
X X X X XX X X X b
X X X X X X X X X a

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Logic Design 20EI38L

Truth table for SIPO

INPUTS OUTPUTS
Clocks Parallel
M Serial D QA QB Qc QD
CIkl CIk2 A B
X X X X
X X X X
X X X
0 X X X X
X a X
X C X X
X X C b a
X X

Truth table for PIPO

INPUTS OUTPUTS
Clocks Parallel
M Serial QB Qc QD
ClIkl CIk2 D Qa
b b C d
1 X X C

Truth table for PISO

INPUTS OUTPUTS
Clocks Parallel
Serial
M
CIk1 CIk2 A C D QA QB Qc QD
X b a b C d
1
X X X X X X X X
X
X X X X X X X X X
0
X X X X X X X X

Johnson CounterRing Counter

Dept. of E&I., S.J.C.E., JSS S&TU,Mysuru 34
Logic Design 20EI3%1
SNZ4LS95
M=0 MODE OA
SN74LS95
CIk1 CLK1 QB
NC HCLK2 QC
CI1LKI
NC
SER QD

kER
Gnd

Gnd Vcc Gnd

forRing Counter
Truth table for Johnson Counter Truth table

QB Qc QD Clk QB Qc QD
Clk QA

1 1 0 0
2 1
2 1 1
1
3 1
1 1 1 4 0
4
5 1
6 0
0
8

Procedure:

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Dept. of E&I., S.J.C.E., JSS S&TU,.Mysuru
 20EI38L
Logic Design

1. Serial-in right-shift operation: terminal

data at the serialinput
a. Connect M(mode control) to logic "0' and apply scrial
starting from the LSB.
QB, Qc, QD.
b. Apply the clkat clock-l terminal and observe the output Qa,
c. Verify the operation as right shift operation. data.
QD after entering the terminal.
d. The output is taken in parallel form at QA, QB, Qc, the clk at clock-I
e. The output in serial form is taken at QD after applying
inputs.
2. Parallel-in shift register.
parallel 4-bit data at A, B, C, D QB, QC
Connect Mto logic '1' and apply the at QA,
a.
terminal and observe theoutputs
b. Apply one clk pulse at clock-2
of1(d)
and QD.
serial form by repeating steps
C. The data can be taken out in parallel and
and 1(e).

Johnson counter:
3. 7495 as Ring and
shown.
a
Connect the circuit as
using SIPO
b. Set the data as 1 000 output.
C. Observe and note down the

Result:

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 20EI38
Logic Design

Experiment 11
SYNCHRONOUS COUNTERS
ASYNCHRONOUS AND

and Synchronous Counters.

Aim:To study asynchronous

Components Required:
IC 7490 4190 (BCD Counter)
IC 7493,74193(Binary Counter)

Theory:
Tocci.
Reference: 1. Digital system design - Ronald J
2. Signetics manual.

Truth table for initial settings

Roay Ro2) Ro1) Ro2) Qu Q QbQa

0
1
0
X X 1

X 0 X 0 Count

Decade Counter

Circuit diagram :
Truth table

Clk QD Oc OB QA
0
SN 7490
0

ck CKA 3
HEKe 4 0

5 0 1
6 (
Gnd
0 1
Gnd
0
9 0

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 20EI38L
LogicDesign

Truth table for initial settings

RÍt Roz QuQe Q Q

1 0
Count

Binary Counter
Truth table
Circuit diagram:
CIk QD QB QA
)
0
2
1
4 0

6 0
1
U1 SN7493 0
0
Clk CKA 0 0
CKB
10
F0(1)
11
12 1 0
13
Grnd 14
Vcc
15

Variable MOD Counter:

7493 as MOD14 counter
counter
7393 as MOD 10

S7492 U1 SN7493
Ci CIk CKA QA
CKB QB

RA2) HRO(1)
RO(2) QD

VCc Gnd

Vcc Gnd
SN7408

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Dept. of E&I., S.J.C.E., JSS
Logic Design
20EI38L
Truth tables:

MOD 10 counter
MOD 14counter
CIk QD Qc QB QA
Clk QD Qc QB QA
0 1 0
2 1 1
3
1
0 1 3 1
4
6 5
7 0 6 0 1
1 7
0

0
10
11
12
13

74190 as Decade up -down counter:

Truth table

EN D/U LOAD CIk Mode

SN74190
X X X Stop count
CTEN Mm
RCO
X X Preset
HCLK QA Up count
LOAD 1
QC
Down count
QD

Note:
For Preset inputs connect RCO to LOAD.

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h cDeSIgn
20E138L

74193 as binary up-downcounter:

SNZ4193
CR Clk up Clkdown L Mode
CLR co
UP 1 X X X Reset to 0
0 Up count
LOAD
Down count
X X Preset
0 Stop

Gnd

BinaryUp Counter Binary Down Counter

CIk QD Qc QB Qa
0 CIk QC QB QA
QD
0 0
2 0 1 0
0 2
4 3
4
5
7 0
)

10 0
0 1 10 0
|2 0
13 12
1 13
14 0
15

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Dept. of E&I., S.J.C.E., JSS S&TU,Mysuru
Logic Design
20EI38L
74193 as MOD 10 Counter: (down counter)

MOD 10Down Counter

SNZ 4193
Clk QD QC QB QA
logic '1"
CLR 1 0 0
1 1 1
CIk DOWN
HLOAD 2 0
Q 3 1 1
0 1 0
1 5 0
6 0
7 1
Grd 8 0
9 0 1
10 0

Procedure:

For 7490/7493:

1. Make connections as shown in the ckt diagram.

2. Connect QA to clkB.
3. Verify the truth table.
For 74190/74193:

1. Make connections as shown in the circuit diagram.

2. Connect lkhzclk to Clkup and logic one to clkdown,observe the counting sequence.
3. Nowconnect 1khz to clkdown and logic one to clkup, observe the counting sequence.
4. Tabulate the results.

Result:

Dept.of E&I., S.J.C.E., JSS S&TU,Mysuru 41

 Experiment 12

SEQUENCE GENERATOR
Aim: Design and testing of sequence generator.
Components Required: IC 7474,7408,7432, Trainer kit.
Theory:
From the prescribed text

Given sequence: 0- 4 -7 -2-3

Circuit diagram:

SN 747 4 SNT74
S 7474

SN743
87432
A

Truth table:

Clk QC QB QA

0
2 1
3
4
 20EI38L
Logic Design

Procedure:
working.
1. Check the D flip flop for its
4, 7, 2, 3.
2. Design the circuit for sequence 0,
sequence.
3. Connect the designed circuit for the given
sequence.
4. Apply the clock pulse and verify the

Result:

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