NAND Gate:

PIN DIAGRAM-IC 7400 SYMBOL

A Y-AB
IC 7400 B
4Vcc
E TRUTH TABLE

Y-AB

NOR Gate:

PIN DIAGRAM-IC7402 SYMBOL

A YA+B
IC7402

TRUTH TABIE

AP
NOT Gate:

PIN DIAGRAM-IC 7404

SYMBOL

IC7404 A
Vcc
Y TRUTH TABLE

A Y=

AND Gate:

PIN DIAGRAM-IC 7408

SYMBOL
A
IC7408 Y-AB
B
Vec
TRUTH TABLE
A B Y-AB
1
0

L
OR Gate:

PIN DIAGRAM-IC 7432 SYMBOL

A Y-A+B
IC 7432 B
Vcc
TRUTH TABLE

A B Y-A+B

0
0 1

X-ORGate:
PIN DIAGRAM-IC 7486 SYMBOL

A Y-

IC 7486 B
Vcc
TRUTH TABLE

B YoRsA
0 0

0
 A BCYY
0 01
0011 1
0101 11
0 1 11
1 00 1
1101 1
1 10
7410 Triple 3 Input NAND 1 11 0

AB C Y
000 0
001 0
0 1
1 1 0
1 0 0 0
101 0
1 1 0
1
-7411 Triple 3 Input AND-
1 11
 Truth Table for 4-input NAND Gate
Input 3 Input 2 Input1 Input 0 Output
1
1

1
1
1

1 1
1 1

1
1
1 0 1 1
1
1
1
1
7420 Dual 4 Input NAND
1
1 1 1 0

AB CD Y
0 0 0
0

0 0
0 0 0
1

1
7421 Dual 4 Input ANDD
 7427 Triple 3 Input NOR-

Truth Table for 7427

Input|input|input|Output
A B C Y

0 0 0

00 1 0
0 1 0
0 1 0
1 0 0 0
1 0 0
1 0
1 1 0
 DUAL D - FLIP FLOP PIN DIAGRAM

(IC 7474)

Vco CLK2 SD2 2 2

RD2 D2

7474 **

RD1 D1 CLKI1 SD1 01 01 GND

LOGIC SYMBOL

10

2 D SD a-5 12D SD a} -
9

11 CP
3 CP
a-8
CD Q-6 wwwww

13

Vcc= PIN 14
GND=PIN 7

TRUTH TABLE

INPUTS OUTPUTS
PR CLR CLK D Q

0 1 X X 1 0

10 X X 0 1
00 X X X X

1 1 1 1 0

1 1 0 0 1
1 10 X ,
 PIN DIAGRAM
JK- FLIP FLOP
DUAL

(IC 74112)

2K 2J 2 PR
VCC 1CLR 2 CLR 2 CK 20

16 | 15 1121 10
PR
CLR Q

L oDCK

PR CLR

1 CK 1K 1J 1 PR 1Q 1Q 2Q GND
LOGIc SYMBOL

10
SD a 5 1 o
1
-cP 13-oP
2 s 12 K cp OP 7

15 14

Vcc= PIN 16s

GND = PIN 83

TRUTH TABLE IEC LOGIC SYMBOL

INPUTS OUTPUTS
CLR PR K| CKQ | FUNCTION
LH X|X X|I CLEAR 1PR 4 N
H
XXX PRESET 1P (5) 10
1CK be1
X|XHH 1CK1K 12IK
10
HHL|
H L H
Qn9n NO CHANGE CLRS
H
L H 2PR (10
20
H H HLL|HL 211
2CK (1
H H| H HL | Qn TOGGLE 12)
2K 220
HHXX n n NO CHANGE
2CLR 1
X Don't Care
 4-Bit Full Adder
(IC 7483)
Pin Diagram

B4 Co GND B A1

7483

A4 3 As B3 V¢c 2 B2 A2

Logic Symbol
3 B2 R1 B0

***
B 10

15 2

Cou .

Truth Table

Input Data A Input Data B Addition

A4 A3 A2 A1 B4 B3 B2 B1 Cout S4 s3 $2 Ssi
1 0 o o 0 1 o 1| o 1| o
o oo1 ooo o
o1
o o1 0 1 1 o 0
o 1 11 o1| 1
1 0

o 1 0 |1
 1-Of-8 Decoder/Demultiplexer (1C 74LS1381
Pin Configuration

VcC O0 O O2 O3 04 05
16 15 14 13 12 1 0
74138

Ap A1 A2 E E2 E 07 GND

LOGIC SYMBOL
3 45 6

1 23
o Aj A2

Oo OO2 Og
15 14 13 12 11
10 9
GNDPIN.16
PIN 8
Truth Table for
741388
INPUTSS
E OUTPUTS
EEsAo A A2 Yo Y1 Y2 Y Ya Ys
X
XXX|X |X YY
H X X HHH H H H HH
HH H
H|HH H HH H
H
X L
xxXHH H H H HH|HH
L H
LH LLL H H|H H H HH HHH
L
HL HL H H HH H H
LH L H L H
L H HH L
H
HLH
H H
H H H H
HL
LHLLL HH H H H L HH HH HH H
HL HH
H H H|H|HL H
L HL H H H H H H H H
L HH
H H HH H H H |HLH
H HL
H- High, L -

Low, X - Don't Care

 8-Input Multiplexer (IC 74151)
Pin Configuration

Vcc
Vcc D4 D5 D6 D7 So S1 S2
S2
|161514 13 12 1 109
IC 74151

Y Y E GND
D3 D2 D1 DO

Logic Symbol Truth Table

74x151
Inputs Output
EN
11 SO (LS)
Select Enable
$2 S1 sol E Y
10 s1 X X X H L H
DO
s2 (MS) L L L DO
D1 D1
5 L L H
DO D2 D2
3D1 L L D3 D3
L HH
2 D2 H L L
D4 D4
D5
D5
D3 HL H
D6 D6
15D4 H H L
D7 D7
H HH
14 D5 E : ENABLE input
13 D6 S0.S1.S2 Select inputs
12 D7 DO-D7: Data inputs
Y, outputs
 Dual 4-Line to 1-Line
Multiplexer (IC 74153)
Pin Configuration

Vcc EN SO D3 D2 D1 DO Zb

74153

EN S1 D3 D2 D1 DO
Za GND

Logic Symbol
74XX153
14
Function Table
1 Select
Inputs Data Inputs Strobe Output
6
1 EN
1 DO SiSo DO D1 D2 D3 EN
Z
D1 Za X X X X H L
1 D2 X X X
3 L L
X X
15 H X
10
2EN L H X X
X
L
2 DO H L X X
L
11 L X
L
2 D1 L-
X X H X
H H
13
2 02 H
L
2 D3 HHX H
Solect inputs A and B ao common
b both sections.
H-High Lovol, L Low Level, X Don't Care
-
-

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