BEKU 1231

ELECTRICAL AND ELECTRONIC ENGINEERING LABORATORY

Experiment 2

Introduction to Digital Logic Circuits, Binary Adders & Flip Flops

Objectives
(i) To investigate the logic gates operations.

(ii) To use test equipment to detect the operation of IC logic gates.

(iii) To become familiar with logic gates.

(iv) To use Boolean theorems to simplify logic circuits.

(v) To investigate the operation of a half adder.

(vi) To investigate the operation of a full adder.

(vii) To investigate the operation of a two-bit ripple adder.

(viii) To verify the operations of various types of flip-flops.

Theoretical Background
Logic gate has been defined as an idealized or physical device which implementing Boolean
function. A logical operation on one or more logic inputs can be performed and produces a
single logic output. Most of the logic gates take an input of two binary values and output a
single binary value of conditions high (1) or low (0) which is represented by different voltage
levels. There are seven basic types of gate which are AND gate, OR gate, NOT gate, XOR
gate, NAND gate, NOR gate, XNOR gate.

A combinational circuit consists of logic gates whose output at any time is determined from
the present combination of inputs without regards to previous input. It performs a specific
information processing operation fully specified logically by a set of Boolean function. It
consists of input variable, logic gates and output variables. The logic circuit accepts signals
from the input and generates signals to the outputs. This process transforms binary
information from the given input to the required output data. For n input variables, there are 2
possible combinations of input values. For each of the input combination, there is one and
only one possible output combination. Each output function is expressed in terms of the n
input variable

The simplest binary adder is called a half adder. Half adder has two input bits and two output
bits. The input variable designates the augends and the addend bits. One output is sum another
is carry. They are represented by S & C. It is necessary to have two output variables because
the result may consist of two binary digits. The carry output is 0 unless both inputs are 1. The
s output represents the least significant bit of the sum. S=A’B+AB’. Half adder has no
provision to add a carry from lower order bits when binary numbers are added.

A flip-flop is an electronic circuit with two stable states that can be used to store binary data.
The stored data can be changed by applying varying inputs. Flip-flops and latches are used
as data storage elements. It is the basic storage element in sequential logic. There are four
basic types of latches and flip-flops: S-R, D, T and J-K. The number of inputs and the way
they change state are the major differences in these flip-flop types.

Methodology
Result
PART A: Introduction to Basic Gates & Integrated Circuit

IC Input, Input, Output, Gate

IAX IBX YX
7408 0 0 0 AND
0 1 0
1 0 0
1 1 1
7432 0 0 0 OR
0 1 1
1 0 1
1 1 1
7400 0 0 1 NAND
0 1 1
1 0 1
1 1 0
7402 0 0 1 NOR
0 1 0
1 0 0
1 1 0
7404 0 - 1 NOT
1 - 0
PART B : Simplification and Combinational Of Logic Gate
Boolean expression for output F,
F = [ AB + ( A+ B ¿ ] [ B+C ]
Simplification of the output expression F,
F = [ AB + ( A+ B ¿ ] [ B+C ]
= [ ( A + B + A B ] ( B+C )
= [ A + B ] ( B+C )
= AB(B+C) Logic Circuit for simplified of expression F
A B C F LED
0 0 0 1 On
0 0 1 0 Off
0 1 0 1 On
0 1 1 1 On
1 0 0 1 On
1 0 1 0 Off
1 1 0 0 Off
1 1 1 0 Off
PART C : Binary Adders

Part 1 : Half Adder Part 2 : Full adder

A B Sum LED Carry LED A B C Carry LED Sum LED
0 0 0 Off 0 Off 0 0 0 0 Off 0 Off
0 1 1 On 0 Off 0 0 1 0 Off 1 On
1 0 1 On 0 Off 0 1 0 0 Off 1 On
1 1 0 Off 1 On 0 1 1 1 On 0 Off
1 0 0 0 Off 1 On
1 0 1 1 On 0 Off
1 1 0 1 On 0 Off
1 1 1 1 On 1 On

Part 3 : Two-bit Ripple Adder

(i) For 01 + 11, (ii) For 10 + 10,
B2 B1 A2 A1 ∑3 ∑2 ∑1 B2 B1 A2 A1 ∑3 ∑2 ∑1
0 1 1 1 1 0 0 1 0 1 0 1 0 0
(iii) For 11 + 11,
B2 B1 A2 A1 ∑3 ∑2 ∑1
1 1 1 1 1 1 0
i) 01 ii) 10 iii) 11
+ 11 + 10 + 11
100 100 110

Part 4 : Additional & Subtraction (Signed Numbers)

(i) For (+2) + (+4),
B4 B3 B2 B1 A4 A3 A2 A1 Carry ∑1 ∑2 ∑3 ∑4
0 0 1 0 0 1 0 0 0 0 1 1 0
(ii) For (+6) + (-3),
B4 B3 B2 B1 A4 A3 A2 A1 Carry ∑1 ∑2 ∑3 ∑4
0 1 1 0 1 1 0 1 1 0 0 1 1
(iii) For (-5) + (-2),
B4 B3 B2 B1 A4 A3 A2 A1 Carry ∑1 ∑2 ∑3 ∑4
1 0 1 0 1 1 1 0 1 1 0 0 1
(i) For (+7) - (+5),
A4 A3 A2 A1 B B B B Carr ∑1 ∑2 ∑3 ∑4
4 3 2 1 y
0 1 1 1 1 0 1 0 1 0 1 0 0
(ii) For (+5) - (-2),
A4 A3 A2 A1 B B B B Carr ∑1 ∑2 ∑3 ∑4
4 3 2 1 y
0 1 0 1 0 0 0 1 0 1 1 1 0
(iii) For (-3) - (-4),
A4 A3 A2 A1 B B B B Carr ∑1 ∑2 ∑3 ∑4
4 3 2 1 y
1 1 0 1 0 0 1 1 1 1 0 0 0
Addition

i) (+2) + (+4) (decimal form)

0010 + 0100 (binary form)
ii) (+6) + (-3) (decimal form)
0110 + 1101 (binary form)
iii) (-5) + (-2) (decimal form)
1011 + 1110 (binary form)
i) 0010 (+2) ii) 0110 (+6)
+0100 (+4) +1101 (-3)
110 (+6) 0011 (+3)

iii) 2nd compliment

+6: 0101 +2: 0010 1011 (-5)

1010 (-6) 1101 (-3) +1110 (-2)
+ 1 (+1) + 1 (+1) 1001 (-7)
1011 (-5) 1110 (-2)

Subtraction:

i) (+7) - (+5) (decimal form)

0111 - 0101 (binary form)
ii) (+5) - (-2) (decimal form)
0101 - 1110 (binary form)
iii) (-3) - (-4) (decimal form)
1101 - 1100 (binary form)

i) 0111 (+7) ii) 0101 (+5)

-0101 (+5) -1110 (-2)
10 (+2) 0111 (+7)

iii) 2nd compliment

+3: 0011 +4: 0100 1101 (-3)

1100 (-4) 1011 (-5) -1100 (-4)
+ 1 (+1) + 1 (+1) 0001 (+1)
1101 (-3) 1100 (-4)

Part D : Flip-Flops
Part 1: The Asynchronous RS Flip-flop Part 2: The Synchronous Flip-flop
Inputs Outputs Inputs Outputs
Set Reset Q Q’ D CLK Q Q
0 0 No change No change 0 ↑ 0 1
0 1 0 1 1 ↑ 1 0
1 0 1 0 1 ↓ 1 0
1 1 0 0

Part 3: J-K Flip-flop

Inputs Outputs Comments

J K CLK Q Q
 0 0 ↓ Q Q No change
0 1 ↓ 0 1 RESET
1 0 ↓ 1 0 SET
1 1 ↓ Q Q Output toggles

Part 1,when Set = Reset = 0, this is the normal resting state for the NOR latch and the output
will remain unchanged. As Q and remained in whatever depends on its previous state to the
occurrence of this input condition. When Set = 0 and Reset = 1, this output for SET is Q = 1
while Q’= 0. When Set = 1 and Reset = 0, this results output for RESET is Q’= 1 while Q = 0.
When Set = 1, Reset = 1, this condition tries to set and reset the latch at the same time, and it
produces Q = Q’ = 0. This input condition should not be used(invalid).

In part 2, Q output will be equal to D whenever CLK input is at positive going edge. It will be
vice versa when negative going transition because D flip-flop can only store 1 single data bit.

For part 3, Q = J while Q = K when J = 0, K = 1 or vice versa. When both J and K = 1, the
output toggles because CLK pulses effect the reversal of the output waveform of Q even
though Q depends on input J and K. There is no changes observed when both J and K were set
to 0 setting J = K = 0 will hold the current state.Thus, the effect of any changes in J and K
occurs at Q only when CLK input is pulsed.

Conclusion
PART A: Introduction to Basic Gates & Integrated Circuit
All the objective for this part A as the introduction to basic gates and integrated circuit has
been achieved as all the types of logic gates has been revealed as the logic gates apply the
same characteristics as stated at the Project Background where AND gate means the
production of both the inputs, OR gate means the addition of both the inputs, while NAND
and NOR gates means the opposite of output after production and addition of both the inputs.
In addition, NOT gate means the reverse of the final output of the logic gates. Therefore, there
are no difference between the result of reality and observations of the outputs.
PART B : Simplification and Combinational Of Logic Gate
The expression are firstly simplified by using Boolean Theorems and also De’ Morgan
Theorem. Then, when the final simplified expression obtained then the logic circuit is tested
where the final simplified expression is the same with the original expression using only 4
ICs. Therefore, the simplification and combinational of logic gates can be done by using
Boolean Theorem and De’ Morgan Theorem.
PART C : Binary Adders
The operation of a half adder is where the input variable designates the augends and the
addend bits and has one output is sum another is carry whereas the full adder is a
combinational circuit that forms the arithmetic sum of three input bits. It consists of three
inputs and two outputs. We became more familiar with the logic circuit and how to do
addition, subtraction and sign numbers.

PART D : Flip-flops

Asynchronous inputs on a flip-flop have control over the outputs (Q and not-Q) regardless of
clock input status. These inputs are called the preset (PRE) and clear (CLR). The preset input
drives the flip-flop to a set state while the clear input drives it to a reset state. It is possible to
drive the outputs of a J-K flip-flop to an invalid condition using the asynchronous inputs,
because all feedback within the multivibrator circuit is overridden.

Reference

[1] Thomas L. Floyd, Digital Fundamentals with PLD Programming, 9th ed, Pearson
Prentice Hall, Upper Saddle River, New Jerseys 2006
[2] Donald P. Leach & Albert Paul Malvino, Digital Principles and Applications, Fifth
ed., McGraw-Hill International Edition. Pg 45-83, 218-223, 282-290