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PHILADELPHIA UNIVERSITY

Faculty of Engineering

Electrical Engineering Department

Eng: zainab Ibrahim awad Al-qaisi

Name: Mohammad mustafa Ababneh

ID: 201910703

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Contents :

Cover page:………………………………………………………...(1)
Objectives:…………………………………………………………...(3)
Equipment (tools):…………..…………………………………...(3)
Procedure:…………..………….………………………………...(4)
Conclusion: …………..………….……………………………….(6)

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Objectives:
 Be able to wire gates to together to produce more complex logic circuits taking into
account limitations on the number of inputs to gates on a chip.
 to become familiar with the state tables for these logic gates.
 to know how to use the pin diagram.
 to know how connect the IC's ( AND , NAND , OR , NOT , XOR) on the board.

Equipment (tools):
1- 7400 NAND
2- 7408 AND
3- 7404 NOT
4- 7402 NOR
5- Wires
6- Logic probe
7- Logic toggle

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Procedure:

Figure 1
Truth table

A B Output
Figure 1 is AND gate.
0 0 0

output is A.B. 0 1 0
1 0 0
1 1 1

Figure 2

Figure 2 is buffer. Inpu Output

t
If the input is 0 then the output is 0 and if the input is 1 then the 0 0
output is equal to 1
1 1
1 input 1 output A ×−1 ×−1= A

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Figure 3

The Implement curcite Figure 3

´
( A B́C´ ¿)+B ¿
B X

Ć+´ A

Figure 4

[ ´ ´ )+ B [ Ć+´ A ] [ B ]
]
X = ( A B́C

Simplification the eqution

[ ´ ´ )+ B [ Ć+´ A ] [ B ] = Á+ B+C

]
X = ( A B́C

output = Á +B +C A B C Out
put
0 0 0 0
0 0 1 0
Truth table: 0 1 0 0
0 1 1 1
1 0 0 0
1 0 5 1 0
1 1 0 0
1 1 1 0
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Conclusion:
In real design, multi-level digital logic is very important science logic elements have
restricted number of inputs.