Chapter 3 Chapter 3:: Topics: Digital Design and Computer Architecture, 2

Chapter
3 Chapter 3 :: Topics
• Introduction
• Latches and Flip‐Flops
Digital Design and Computer Architecture, 2nd Edition
• Synchronous Logic Design
David Money Harris and Sarah L. Harris
• Finite State Machines
• Timing of Sequential Logic
• Parallelism
Chapter 3 <1> Chapter 3 <2>
Introduction Sequential Circuits
• Outputs of sequential logic depend on current • Give sequence to events
and prior input values – it has memory. • Have memory (short-term)
• Some definitions: • Use feedback from output to input to store
– State: all the information about a circuit necessary information
to explain its future behavior
– Latches and flip‐flops: state elements that store
one bit of state
– Synchronous sequential circuits: combinational
logic followed by a bank of flip‐flops
1
State Elements Bistable Circuit
• The state of a circuit influences its future • Fundamental building block of other state
behavior elements
• State elements store state • Two outputs: Q, Q
– Bistable circuit • No inputs
– SR Latch
I1 Q
– D Latch I2
Q
I1
Q
– D Flip-flop
I2 Q
Bistable Circuit Analysis SR (Set/Reset) Latch

• Consider the two possible cases: • SR Latch R
N1 Q
– Q = 0: I1
0
Q
1
then Q = 1, Q = 0 (consistent)
0 1
I2 Q
N2 Q
– Q = 1: S
• Consider the four possible cases:
1
then Q = 0, Q = 1 (consistent) 0
I1 Q
– S = 1, R = 0
1 0
I2 Q
– S = 0, R = 1
• Stores 1 bit of state in the state variable, Q (or Q) – S = 0, R = 0
• But there are no inputs to control the state – S = 1, R = 1
2
SR Latch Analysis SR Latch Analysis
– S = 1, R = 0: R
0
1
– S = 0, R = 0: Qprev = 0 Qprev = 1
N1 Q
then Q = 1 and Q = 0 0 then Q = Qprev R
0
N1
0
Q
R
0
N1
1
Q
0
0
1 N2 Q
S
0 N2 Q 0 N2 Q
S S
– S = 0, R = 1: 1
R
N1
0
Q – S = 1, R = 1: R
1
0
then Q = 1 and Q = 0 1 0
N1 Q
then Q = 0, Q = 0
0
1 0
0 N2 Q 0
S 1 N2 Q
S
SR Latch Analysis SR Latch Symbol
– S = 0, R = 0: Qprev = 0 Qprev = 1 • SR stands for Set/Reset Latch
then Q = Qprev R
0
0 R
0 – Stores one bit of state (Q)
N1 Q N1 Q
– Memory! • Control what value is being stored with S, R
inputs
0 N2 Q 0 N2 Q SR Latch
S S
– Set: Make the output 1 Symbol
(S = 1, R = 0, Q = 1)
– S = 1, R = 1: R
1
N1
0
Q R Q
0 – Reset: Make the output 0
then Q = 0, Q = 0
0 (S = 0, R = 1, Q = 0) S Q
– Invalid State S
1 N2
0
Q
Q ≠ NOT Q
3
D Latch D Latch Internal Circuit
• Two inputs: CLK, D CLK R R Q Q CLK
D
– CLK: controls when the output changes
D Q
– D (the data input): controls what the output changes to D
S S Q Q
Q
• Function D Latch
– When CLK = 1, Symbol
D passes through to Q (transparent) CLK D D S R Q Q
CLK
0 X
– When CLK = 0,
D Q 1 0
Q holds its previous value (opaque) 1 1
Q
• Avoids invalid case when
Q ≠ NOT Q
D Latch Internal Circuit D Flip‐Flop
CLK • Inputs: CLK, D D Flip-Flop
D
R R Q Q CLK Symbols
• Function
S
D Q
D
S Q Q – Samples D on rising edge of CLK
Q • When CLK rises from 0 to 1, D D Q
passes through to Q Q
CLK D D S R Q Q • Otherwise, Q holds its previous
0 X X 0 0 Qprev Qprev value
1 0 1 0 1 0 1 – Q changes only on rising edge of
1 1 0 1 0 1 0 CLK
• Called edge-triggered
• Activated on the clock edge
4
D Flip‐Flop Internal Circuit D Latch vs. D Flip‐Flop
• Two back-to-back latches (L1 and L2) controlled by CLK
complementary clocks D Q D Q
CLK
• When CLK = 0 Q Q
– L1 is transparent
– L2 is opaque CLK CLK
– D passes through to N1 N1
D D Q D Q Q CLK
• When CLK = 1 L1 Q L2 Q Q
D
– L2 is transparent
– L1 is opaque Q (latch)
– N1 passes through to Q
• Thus, on the edge of the clock (when CLK rises from 0 1) Q (flop)
– D passes through to Q
D Latch vs. D Flip‐Flop Registers
CLK
CLK
D Q D Q
D0 D Q Q0
Q Q
CLK
D1 D Q Q1 4 4
CLK
D3:0 Q 3:0
D
D2 D Q Q2
Q (latch)
Q (flop)
D3 D Q Q3
5
Enabled Flip‐Flops Resettable Flip‐Flops
• Inputs: CLK, D, EN • Inputs: CLK, D, Reset
– The enable input (EN) controls when new data (D) is stored • Function:
• Function – Reset = 1: Q is forced to 0
– EN = 1: D passes through to Q on the clock edge – Reset = 0: flip-flop behaves as ordinary D flip-flop
– EN = 0: the flip-flop retains its previous state
Internal Symbols
Circuit
Symbol
EN CLK
0
D Q
D Q Q D Q r
D 1 Reset
EN
Resettable Flip‐Flops Resettable Flip‐Flops
• Two types: • Two types:
– Synchronous: resets at the clock edge only – Synchronous: resets at the clock edge only
– Asynchronous: resets immediately when Reset = 1 – Asynchronous: resets immediately when Reset = 1
• Asynchronously resettable flip-flop requires • Asynchronously resettable flip-flop requires
changing the internal circuitry of the flip-flop changing the internal circuitry of the flip-flop
• Synchronously resettable flip-flop? • Synchronously resettable flip-flop?
Internal
Circuit
CLK
D
D Q Q
Reset
6
Settable Flip‐Flops Sequential Logic
• Inputs: CLK, D, Set • Sequential circuits: all circuits that aren’t
• Function: combinational
– Set = 1: Q is set to 1 • A problematic circuit:
– Set = 0: the flip-flop behaves as ordinary D flip-flop X
X Y Z
Y
Symbols Z
0 1 2 3 4 5 6 7 8 time (ns)
D Q
s
Set
Sequential Logic Synchronous Sequential Logic Design
• Sequential circuits: all circuits that aren’t • Breaks cyclic paths by inserting registers
combinational • Registers contain state of the system
• State changes at clock edge: system synchronized to the
• A problematic circuit: clock
X • Rules of synchronous sequential circuit composition:
X Y Z
Y – Every circuit element is either a register or a combinational circuit
Z
– At least one circuit element is a register
0 1 2 3 4 5 6 7 8 time (ns) – All registers receive the same clock signal
– Every cyclic path contains at least one register
• No inputs and 1-3 outputs
• Two common synchronous sequential circuits
• Astable circuit, oscillates
– Finite State Machines (FSMs)
• Period depends on inverter delay
– Pipelines
• It has a cyclic path: output fed back to input
7
Finite State Machine (FSM) Finite State Machines (FSMs)
• Consists of: CLK • Next state determined by current state and inputs
• Two types of finite state machines differ in output logic:
– State register S’
Next
S
Current – Moore FSM: outputs depend only on current state
• Stores current state State State – Mealy FSM: outputs depend on current state and inputs
• Loads next state at clock edge Moore FSM
– Combinational logic M next

CLK
next k state
k state output N
inputs
• Computes the next state state
logic
logic
outputs
• Computes the outputs

Mealy FSM
Next State Output
Logic Logic CLK
M next
next k k state N
CL Next
State
CL Outputs inputs state
logic
state output
logic outputs
FSM Example FSM Black Box
• Traffic light controller • Inputs: CLK, Reset, TA, TB
– Traffic sensors: TA, TB (TRUE when there’s traffic) • Outputs: LA, LB
– Lights: LA, LB CLK
Bravado
Dining
Hall
LB
TA Traffic LA
LA TB Light
LA
TB Controller LB
Academic TA TA Ave.
Labs TB LB Dorms
Reset
Blvd.
Fields
8
FSM State Transition Diagram FSM State Transition Diagram
• Moore FSM: outputs labeled in each state • Moore FSM: outputs labeled in each state
• States: Circles • States: Circles Reset
T A
Reset
• Transitions: Arcs S0 • Transitions: Arcs S0 T S1 A
LA: green LA: green LA: yellow

LB: red LB: red LB: red
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB
FSM State Transition Table FSM State Transition Table
Current Next Current Next

State Inputs State State Inputs State
S TA TB S' S TA TB S'
S0 0 X S0 0 X S1
S0 1 X S0 1 X S0
S1 X X S1 X X S2
S2 X 0 S2 X 0 S3
S2 X 1 S2 X 1 S2
S3 X X S3 X X S0
9
FSM Encoded State Transition Table FSM Encoded State Transition Table
Current State Inputs Next State Current State Inputs Next State
S1 S0 TA TB S'1 S'0 State Encoding S1 S0 TA TB S'1 S'0 State Encoding
0 0 0 X 0 0 0 X 0 1
S0 00 S0 00
0 0 1 X 0 0 1 X 0 0
0 1 X X S1 01 0 1 X X 1 0 S1 01
1 0 X 0 S2 10 1 0 X 0 1 1 S2 10
1 0 X 1 S3 11 1 0 X 1 1 0 S3 11
1 1 X X 1 1 X X 0 0
S'1 = S1  S0
S'0 = S1S0TA + S1S0TB
FSM Output Table FSM Output Table
Current State Outputs Current State Outputs

Output Encoding Output Encoding
S1 S0 LA1 LA0 LB1 LB0 S1 S0 LA1 LA0 LB1 LB0
0 0 green 00 0 0 0 0 1 0 green 00
0 1 yellow 01 0 1 0 1 1 0 yellow 01
1 0 1 0 1 0 0 0
red 10 red 10
1 1 1 1 1 0 0 1
LA1 = S1
LA0 = S1S0
LB1 = S1
LB0 = S1S0
10
FSM Schematic: State Register FSM Schematic: Next State Logic
CLK CLK
S'1 S1 S'1 S1
S'0 S0 TA S'0 S0
r r
TB Reset
Reset
S1 S0
state register
inputs next state logic state register
FSM Schematic: Output Logic FSM Timing Diagram
C yc le 1 C y c le 2 C y c le 3 C y c le 4 C y c le 5 C yc le 6 C y c le 7 C y c le 8 C y c le 9 C yc le 1 0
CLK LA1 CLK
R eset
S'1 S1
TA
LA0 TB
S ' 1:0 ?? S0 (0 0 ) S1 (0 1 ) S2 (1 0 ) S3 (1 1 ) S0 (0 0 ) S1 (0 1 )
TA S'0 S0 S 1 :0 ?? S0 (0 0 ) S1 (0 1 ) S2 (1 0 ) S3 (1 1 ) S0 (0 0 )
LB1
r L A 1 :0 ?? G re e n (0 0 ) Y e llo w (0 1 ) R e d (1 0 ) G re e n (0 0 )
L B 1 :0 ?? R e d (1 0 ) G re e n (0 0 ) Y e llo w (0 1 ) R e d (1 0 )
TB Reset
S1 S0 LB0 0 5 10 15 20 25 30 35 40 45 t (s e c )
TA
Reset
S0 TA S1
LA: green LA: yellow
inputs next state logic state register output logic outputs LB: red LB: red
S3 S2
LA: red LA: red
LB: yellow LB: green
TB
TB
11
FSM State Encoding Moore vs. Mealy FSM
• Binary encoding: • Alyssa P. Hacker has a snail that crawls down a paper tape
with 1’s and 0’s on it. The snail smiles whenever the last two
– i.e., for four states, 00, 01, 10, 11 digits it has crawled over are 01. Design Moore and Mealy
• One-hot encoding FSMs of the snail’s brain.
– One state bit per state
– Only one state bit HIGH at once
– i.e., for 4 states, 0001, 0010, 0100, 1000
– Requires more flip-flops
– Often next state and output logic is simpler
State Transition Diagrams Moore FSM State Transition Table
Moore FSM
Current
Reset
0 1 State Inputs Next State State Encoding
S0
0
S1
0
S2
1
S1 S0 A S'1 S'0 S0 00
1 0 0 0 0 0
1
0 0 1 S1 01
0 1 0 S2 10
Mealy FSM
0 1 1
Reset
0/0
1 0 0
S0 S1
1 0 1
1/0 0/0
1/1
Mealy FSM: arcs indicate input/output
12
Moore FSM State Transition Table Moore FSM Output Table
Current
State Inputs Next State State Encoding Current State Output
S1 S0 A S'1 S'0 S0 00 S1 S0 Y
0 0 0 0 1
S1 01 0 0
0 0 1 0 0
0 1 0 0 1 0 1
S2 10
0 1 1 1 0 1 0
1 0 0 0 1
Y = S1
1 0 1 0 0
S1’ = S0A
S0’ = A
Moore FSM Output Table Mealy FSM State Transition & Output Table
Current Next
Current State Output State Input State Output
S0 A S'0 Y State Encoding
S1 S0 Y
0 0
0 0 0 0 1 S0 00
0 1 0 1 0 S1 01
1 0 1 1 1
Y = S1
13
Mealy FSM State Transition & Output Table Moore FSM Schematic
Current Next A CLK

State Input State Output
S'1 S1
S0 A S'0 Y State Encoding Y
0 0 1 0
0 1 0 0 S0 00
1 0 1 0 S1 01 S'0 S0
1 1 0 1
r
Reset
Mealy FSM Schematic Moore & Mealy Timing Diagram
A Cycle 1 Cycle 2 Cycle 3 Cycle 4 Cycle 5 Cycle 6 Cycle 7 Cycle 8 Cycle 9 Cycle 10 Cycle 11
CLK
CLK Reset
S'0 S0 Y
A 0 1 0 1
Moore Machine
1 0 1 1 1
S ?? S0 S1 S2 S1 S2 S0 S1 S2 S0
Y
Mealy Machine
r S ?? S0 S1 S0 S1 S0 S1 S0
Reset
14
Factoring State Machines Parade FSM
• Break complex FSMs into smaller interacting Unfactored FSM P
R Controller LA
FSMs TA FSM LB
TB
• Example: Modify traffic light controller to have
Parade Mode.
Factored FSM P
– Two more inputs: P, R Mode
FSM
R
– When P = 1, enter Parade Mode & Bravado Blvd
M
light stays green
TA Lights LA
– When R = 1, leave Parade Mode TB FSM LB
Controller
FSM
Unfactored FSM Factored FSM

P TA
P TA TA
R TA R TA Reset
Reset TA
P TA S0 S1
S0 S1 R TA
R TA LA: green LA: yellow
LA: green LA: yellow S4 S5
P LB: red LB: red
LB: red LB: red LA: green LA: yellow
LB: red R LB: red
P
P TA
P
R P
Reset
P R P
P TB R S3 S2
S3 S2 S0 S1
LA: red LA: red
LA: red LA: red S7 S6 M: 0 M: 1
LB: yellow LB: green R
LB: yellow LB: green LA: red LA: red MTB
P TB LB: yellow LB: green
M + TB R
P R
Lights FSM Mode FSM
R TB
R TB
15
FSM Design Procedure Timing
• Identify inputs and outputs
• Flip-flop samples D at clock edge
• Sketch state transition diagram
• Write state transition table • D must be stable when sampled
• Select state encodings • Similar to a photograph, D must be stable
• For Moore machine: around clock edge
– Rewrite state transition table with state encodings
• If not, metastability can occur
– Write output table
• For a Mealy machine:
– Rewrite combined state transition and output table with state
encodings
• Write Boolean equations for next state and output logic
• Sketch the circuit schematic
Input Timing Constraints Output Timing Constraints
• Setup time: tsetup = time before clock edge data must be • Propagation delay: tpcq = time after clock edge that the
stable (i.e. not changing) output Q is guaranteed to be stable (i.e., to stop changing)
• Hold time: thold = time after clock edge data must be stable • Contamination delay: tccq = time after clock edge that Q
• Aperture time: ta = time around clock edge data must be might be unstable (i.e., start changing)
stable (ta = tsetup + thold)
CLK
CLK Q
tccq
D tpcq
tsetup thold
ta
16
Dynamic Discipline Dynamic Discipline
• Synchronous sequential circuit inputs must be • The delay between registers has a
stable during aperture (setup and hold) time minimum and maximum delay, dependent
around clock edge on the delays of the circuit elements
CLK CLK
• Specifically, inputs must be stable Q1 D2
CL
– at least tsetup before the clock edge
R1 R2
– at least until thold after the clock edge (a)
Tc
CLK
Q1
D2
(b)
Setup Time Constraint Setup Time Constraint
• Depends on the maximum delay from register R1 • Depends on the maximum delay from register R1
through combinational logic to R2 through combinational logic to R2
• The input to register R2 must be stable at least tsetup • The input to register R2 must be stable at least tsetup
before clock edge before clock edge
CLK CLK CLK CLK
Q1 D2 Q1 D2
CL
Tc ≥ CL
Tc ≥ tpcq + tpd + tsetup
R1 R2 R1 R2
Tc Tc tpd ≤
CLK CLK
Q1 Q1
D2 D2
tpcq tpd tsetup tpcq tpd tsetup
17
Setup Time Constraint Hold Time Constraint
• Depends on the maximum delay from register R1 • Depends on the minimum delay from register R1
through combinational logic to R2 through the combinational logic to R2
• The input to register R2 must be stable at least tsetup • The input to register R2 must be stable for at least
before clock edge thold after the clock edge
CLK CLK CLK CLK
Q1 D2 Q1 C D2
CL
Tc ≥ tpcq + tpd + tsetup L
thold <
R1 R2 R1 R2
Tc tpd ≤ Tc – (tpcq + tsetup)
CLK
CLK
Q1
Q1
D2
D2
tccq tcd
tpcq tpd tsetup
thold
Hold Time Constraint Hold Time Constraint
• Depends on the minimum delay from register R1 • Depends on the minimum delay from register R1
through the combinational logic to R2 through the combinational logic to R2
• The input to register R2 must be stable for at least • The input to register R2 must be stable for at least
thold after the clock edge thold after the clock edge
CLK CLK CLK CLK
Q1 C D2 Q1 C D2
L
thold < tccq + tcd L
thold < tccq + tcd
R1 R2 R1 R2
tcd > tcd > thold - tccq
CLK CLK
Q1 Q1
D2 D2
tccq tcd tccq tcd
thold thold
18
Timing Analysis Timing Analysis
CLK CLK Timing Characteristics CLK CLK Timing Characteristics
A A
tccq = 30 ps tccq = 30 ps
B
tpcq = 50 ps B
tpcq = 50 ps
tsetup = 60 ps tsetup = 60 ps
X' X X' X
C thold = 70 ps C thold = 70 ps
Y' Y Y' Y
D D
per gate
per gate
tpd = 35 ps tpd = 35 ps
tcd = 25 ps tcd = 25 ps
tpd = tpd = 3 x 35 ps = 105 ps
tcd = tcd = 25 ps
Setup time constraint: Hold time constraint: Setup time constraint: Hold time constraint:
Tc ≥ tccq + tcd > thold ? Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tcd > thold ?
fc = fc = 1/Tc = 4.65 GHz (30 + 25) ps > 70 ps ? No!
Timing Analysis Timing Analysis
Add buffers to the short paths: Timing Characteristics Add buffers to the short paths: Timing Characteristics
CLK CLK tccq = 30 ps CLK CLK tccq = 30 ps
A A
tpcq = 50 ps tpcq = 50 ps
B tsetup = 60 ps B tsetup = 60 ps
C
X' X thold = 70 ps C
X' X thold = 70 ps
Y' Y Y' Y
D D
per gate
per gate
tpd = 35 ps tpd = 35 ps
tcd = 25 ps tcd = 25 ps
tpd = tpd = 3 x 35 ps = 105 ps
tcd = tcd = 2 x 25 ps = 50 ps
Setup time constraint: Hold time constraint: Setup time constraint: Hold time constraint:
Tc ≥ tccq + tcd > thold ? Tc ≥ (50 + 105 + 60) ps = 215 ps tccq + tcd > thold ?
fc = fc = 1/Tc = 4.65 GHz (30 + 50) ps > 70 ps ? Yes!
19
Clock Skew Setup Time Constraint with Skew
• The clock doesn’t arrive at all registers at same time • In the worst case, CLK2 is earlier than CLK1
• Skew: difference between two clock edges CLK1 CLK2
• Perform worst case analysis to guarantee dynamic Q1 C
L
D2
discipline is not violated for any register – many R1 R2
registers in a system! Tc
delay CLK CLK1
Tc ≥
CLK1 CLK2
CLK2
Q1 C D2
L
R1 R2
Q1
t skew D2
CLK1
tpcq tpd tsetup tskew
CLK2
CLK
Setup Time Constraint with Skew Setup Time Constraint with Skew
• In the worst case, CLK2 is earlier than CLK1 • In the worst case, CLK2 is earlier than CLK1
CLK1 CLK2 CLK1 CLK2
Q1 C D2 Q1 C D2
L L
R1 R2 R1 R2
Tc Tc
CLK1 CLK1
Tc ≥ tpcq + tpd + tsetup + tskew Tc ≥ tpcq + tpd + tsetup + tskew
CLK2 tpd ≤ CLK2 tpd ≤ Tc – (tpcq + tsetup + tskew)
Q1 Q1
D2 D2
tpcq tpd tsetup tskew tpcq tpd tsetup tskew
20
Hold Time Constraint with Skew Hold Time Constraint with Skew
• In the worst case, CLK2 is later than CLK1 • In the worst case, CLK2 is later than CLK1
CLK1 CLK2 CLK1 CLK2
Q1 CL D2 Q1 CL D2
R1 R2 R1 R2
CLK1 CLK1
CLK2
tccq + tcd > CLK2
tccq + tcd > thold + tskew
Q1 Q1 tcd >
D2 D2
tccq tcd tccq tcd
tskew thold tskew thold
Hold Time Constraint with Skew Violating the Dynamic Discipline
• In the worst case, CLK2 is later than CLK1 • Asynchronous (for example, user)
tsetup thold
CLK1 CLK2 inputs might violate the dynamic
Q1 CL D2 discipline CLK
button
R1 R2 CLK taperture
D D
Case I
CLK1 Q
CLK2
tccq + tcd > thold + tskew Q
Q1 tcd > thold + tskew – tccq

D
Case II
D2 Q
tccq tcd
Case III
D
tskew thold ???
Q
21
Metastability Flip‐Flop Internals
• Bistable devices: two stable states, and a metastable • Flip-flop has feedback: if Q is somewhere between
state between them 1 and 0, cross-coupled gates drive output to either
• Flip-flop: two stable states (1 and 0) and one rail (1 or 0) R
N1 Q
metastable state
• If flip-flop lands in metastable state, could stay there S
N2 Q
for an undetermined amount of time

• Metastable signal: if it hasn’t resolved to 1 or 0
metastable • If flip-flop input changes at random time, probability
that output Q is metastable after waiting some time, t:
stable stable P(tres > t) = (T0/Tc ) e-t/τ
tres : time to resolve to 1 or 0

T0, τ : properties of the circuit
Metastability Synchronizers
• Intuitively: • Asynchronous inputs are inevitable (user interfaces,
– T0/Tc: probability input changes at a bad time (during aperture) systems with different clocks interacting, etc.)
P(tres > t) = (T0/Tc ) e-t/τ • Synchronizer goal: make the probability of failure (the
output Q still being metastable) low
– τ: time constant for how fast flip-flop moves away from • Synchronizer cannot make the probability of failure 0
metastability
P(tres > t) = (T0/Tc ) e-t/τ
CLK
• In short, if flip-flop samples metastable input, if you wait
SYNC
long enough (t), the output will have resolved to 1 or 0 D Q
with high probability.
22
Synchronizer Internals Synchronizer Probability of Failure
• Synchronizer: built with two back-to-back flip-flops For each sample, probability of failure is:
• Suppose D is transitioning when sampled by F1 P(failure) = (T0/Tc ) e-(Tc - t
setup
)/τ
• Internal signal D2 has (Tc - tsetup) time to resolve to 1 CLK CLK

or 0 CLK CLK
D
D2
Q
D2
D Q
F1 F2
F1 F2 Tc
Tc
CLK
CLK
D2 metastable
D2 metastable
Q Q
tres tsetup tpcq tres tsetup tpcq

Synchronizer Mean Time Between Failures Example Synchronizer
CLK CLK
• If asynchronous input changes once per second, D
D2
Q
probability of failure per second is P(failure).
F1 F2
• If input changes N times per second, probability of failure
per second is: • Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps
T0 = 150 ps tsetup = 100 ps
P(failure)/second = (NT0/Tc) e-(Tc - t
setup
)/τ
N = 1 events per second
• What is the probability of failure? MTBF?
• Synchronizer fails, on average, 1/[P(failure)/second]
• Called mean time between failures, MTBF:
MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc - t

setup
)/τ
23
Example Synchronizer Parallelism
CLK CLK
D
D2
Q • Two types of parallelism:
F1 F2 – Spatial parallelism
• duplicate hardware performs multiple tasks at once
• Suppose: Tc = 1/500 MHz = 2 ns τ = 200 ps
T0 = 150 ps tsetup = 100 ps – Temporal parallelism
N = 1 events per second • task is broken into multiple stages
• What is the probability of failure? MTBF?
• also called pipelining
P(failure) = (150 ps/2 ns) e-(1.9 ns)/200 ps
= 5.6 × 10-6 • for example, an assembly line
P(failure)/second = 10 × (5.6 × 10-6 )
= 5.6 × 10-5 / second
MTBF = 1/[P(failure)/second] ≈ 5 hours
Parallelism Definitions Parallelism Example
• Token: Group of inputs processed to produce • Ben Bitdiddle bakes cookies to celebrate traffic light
controller installation
group of outputs
• 5 minutes to roll cookies
• Latency: Time for one token to pass from • 15 minutes to bake
start to end • What is the latency and throughput without parallelism?
• Throughput: Number of tokens produced
per unit time
Parallelism increases throughput
24
Parallelism Example Parallelism Example
• Ben Bitdiddle bakes cookies to celebrate traffic light • What is the latency and throughput if Ben
controller installation
uses parallelism?
• 5 minutes to roll cookies
• 15 minutes to bake
– Spatial parallelism: Ben asks Allysa P. Hacker to
help, using her own oven
• What is the latency and throughput without parallelism?
– Temporal parallelism:
Latency = 5 + 15 = 20 minutes = 1/3 hour • two stages: rolling and baking
Throughput = 1 tray/ 1/3 hour = 3 trays/hour • He uses two trays
• While first batch is baking, he rolls the
second batch, etc.
Spatial Parallelism Spatial Parallelism
Latency: Latency:
time to time to
first tray first tray
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
Time Time
Tray 1 Ben 1 Ben 1 Tray 1 Ben 1 Ben 1
Parallelism
Roll
Parallelism
Roll
Spatial
Spatial
Tray 2 Alyssa 1 Alyssa 1 Tray 2 Alyssa 1 Alyssa 1
Bake Bake
Legend Legend
Tray 4 Alyssa 2 Alyssa 2 Tray 4 Alyssa 2 Alyssa 2
Latency = ? Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = ? Throughput = 2 trays/ 1/3 hour = 6 trays/hour
25
Temporal Parallelism Temporal Parallelism
Latency: Latency:
time to time to
first tray first tray
0 5 10 15 20 25 30 35 40 45 50 0 5 10 15 20 25 30 35 40 45 50
Time Time
Parallelism
Tray 1 Ben 1 Ben 1
Parallelism
Tray 1 Ben 1 Ben 1
Temporal
Temporal
Latency = ? Latency = 5 + 15 = 20 minutes = 1/3 hour

Throughput = ? Throughput = 1 trays/ 1/4 hour = 4 trays/hour
Using both techniques, the throughput would be 8 trays/hour
26

Chapter 3 Chapter 3:: Topics: Digital Design and Computer Architecture, 2

Uploaded by

Document Information

Original Title

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

Chapter 3 Chapter 3:: Topics: Digital Design and Computer Architecture, 2

Uploaded by

Copyright:

Available Formats

Chapter

Bistable Circuit Analysis SR (Set/Reset) Latch

– Combinational logic M next

• Computes the outputs

LA: green LA: green LA: yellow

Current Next Current Next

Current State Outputs Current State Outputs

inputs next state logic state register

CLK LA1 CLK

Mealy FSM: arcs indicate input/output

Current Next A CLK

Unfactored FSM Factored FSM

tpcq tpd tsetup tskew tpcq tpd tsetup tskew

tskew thold tskew thold

Q1 tcd > thold + tskew – tccq

for an undetermined amount of time

tres : time to resolve to 1 or 0

• In short, if flip-flop samples metastable input, if you wait

• Internal signal D2 has (Tc - tsetup) time to resolve to 1 CLK CLK

tres tsetup tpcq tres tsetup tpcq

MTBF = 1/[P(failure)/second] = (Tc/NT0) e(Tc - t

Parallelism increases throughput

Latency = ? Latency = 5 + 15 = 20 minutes = 1/3 hour

Tray 1 Ben 1 Ben 1

Tray 3 Ben 3 Ben 3 Tray 3 Ben 3 Ben 3

Latency = ? Latency = 5 + 15 = 20 minutes = 1/3 hour

Using both techniques, the throughput would be 8 trays/hour

You might also like