UNIT – I

1. Explain in detail about the steps involved in CMOS IC fabrication process with essential
diagrams. June 2018 (R15)
2. Draw the Ids-Vds relationship curve and discuss in detail about its role in the MOS design
equations. June 2018 (R15)
3. Explain clearly about NMOS fabrication process flow with neat diagrams.
4. Draw the V-I characteristics of MOSFET and prove that Ids is linear function of Vds. June
2018 (R15)
5. When the gate to source voltage VGS of a MOSFET with threshold voltage of 400 mv,
working in saturation is 900 mv, the drain current is observed to be 1 mA and assuming that
the MOSFET is operating at saturation, calculate the drain current for an applied VGS of
1400 mv. June 2018 (R15)
6. Explain NMOS fabrication process flow with neat diagrams. June 2017 (R13)
7. Draw V-I characteristics of NMOS transistor. Explain its operation. Derive the drain to
source current equation in saturation and resistive region. June 2017 (R13)
8. (a) Explain clearly about n-well CMOS fabrication process with neat diagrams. Dec 2016
(b) Explain the operation NMOS enhancement mode transistor with neat diagrams.
9. (a) Explain about various IC technologies. June 2014 (R09)
(b) Explain the term output conductance using necessary equations.
10. Explain the latch-up effect in CMOS inverter. June 2015(R09)
11. (a) Why is NMOS technology more preferred than PMOS technology? June 2016 (R09)
(b) Compare CMOS and BI-CMOS technology.
12. (a) Explain the operation of CMOS inverter with a neat diagram. June 2017 (R09)
(b) Find the drain-to-source current versus voltage relationship of Ids Vs Vds of n-MOS
Transistor.
13. Draw the V-I characteristics of MOSFET and prove that Ids is linear function of Vds.
14. Explain the term MOS Transistor Threshold voltage.

PART-B

1. Illustrate in details various processing steps involved in the fabrication of CMOS transistor
with necessary diagrams.
2. Explain about basic steps in IC fabrication.
3. Explain the operation of BiCMOS inverter with a neat diagram.
4. Explain clearly about SOI fabrication process with neat diagrams.
5. Determine pull up to pull down ratio for an NMOS inverter driven through one or more pass
transistors.

UNIT – II
1. (a) Derive the expression for resistance estimation in VLSI circuits. June 2018 (R15)
(b) Write short notes on driving large capacitive loads. June 2018 (R15)
2. (a) Explain the 2μm CMOS design rules for contacts and transistors. June 2018 (R15)
(b) Briefly discuss about scaling of MOS circuits and its limitations. June 2018 (R15)
3. (a) Define fan-in and fan-out. Explain their effects on propagation delay. June 2018 (R15)
(b) What do you mean by inverter delay? Explain.
4. Design a stick and layout diagram for CMOS inverter and two inputs NMOS NAND gate.
5. Design a stick and layout diagram for CMOS inverter and two input n-MOS NAND June
2017 (R13)
6. (a) Define fan-in and fan-out. Explain their effects on propagation delay. June 2017 (R13)
(b)What do you mean by inverter delay? Explain.

7. Draw a stick diagram for three input n-MOS NAND and NOR gates. Dec 2016 (R13)
8. (a) Derive the expression for rise time, fall time and propagation delay of CMOS inverter.
(b) What is MOS scaling? What are the limitations of scaling? June 2016 (R09)

9. (a) Explain about wiring capacitance.

(b) Draw a stick diagram for three input P-MOS NAND and NOR gates. June 2016 (R09)

10. Draw a stick diagram for two input C-MOS NAND gate. June 2014 (R09)
11. Calculate gate capacitance value of 2 μm technology minimum sized transistor with gate to
channel capacitance value of 8 X 104 pF/ohm μm2. June 2014 (R09)
12. Draw the CMOS NOR gate & its physical layout with stick diagram. Jan 2015 (R09)

PART-II

1. What is a stick diagram and explain different symbols used for components in stick
diagram.
2. Design a layout diagram for PMOS logic Y= (AB+CD)’
3. Design a stick and layout diagram for CMOS logic Y= (A+B) (C+D)
4. What are the different types of Lambda based design rules?
5. What are the different types of scaling factors for various parameters of MOS Circuit?

UNIT – III
1. With a detailed step by step process, design and draw the AND-OR-INVERT form
complex gates in CMOS logic for the output equation. June 2018 (R15)

2. Give a detailed note on floor-planning and placement in the physical design flow of a
CMOS circuit design. June 2018 (R15)
3. What are the alternate gate circuits are available? Explain them with suitable sketch. June
2018 (R15)
4. Discuss about the floor planning. June 2018 (R15)
5. (a) Explain clocked CMOS logic, domino logic and n-p CMOS logic. June 2017 (R09)
(b)Discuss the scaling factors for the following device parameters:
(i) Gate capacitance. (ii) Maximum operating frequency. (iii) Current density.
(iv) Power dissipation per gate.

6. Write short notes about the following: Dec 2016(R13)

(a)Pseudo nMOS logic (b) Domino-Logic
7. Discuss about the floor planning Dec 2016 (R13)
8. What are the alternate gate circuits are available, explain Dynamic CMOS Logic with
suitable sketch? June 2017( R13)
9. Explain about VLSI physical design flow June 2017 (R13)
10. Discuss about the Transmission gate with diagram Jan 2015 (R09)
11. With the help of a block diagram, explain the AOI Complex logic gates. June 2014 (R09)
12. (a) Explain about Clock and power routing Dec 2016 (R13)
(b) Why scaling is required? Write the scaling factors for different types of device
Parameters? Dec 2016 (R13)

PART-B

1. What are the alternate gate circuits are available, explain Domino CMOS Logic with
suitable sketch?
2. Explain CCMOS Logic with suitable sketch?

UNIT – IV
1. Explain about any one multiplier architecture in VLSI design. What are the challenging
issues to be considered for the same? June 2018 (R15)
2. Illustrate with neat architecture diagram and explain about various functional blocks of
Field Programmable Gate Array (FPGAs). June 2018 (R15)
3. Explain the working principle of 6-transistor static RAM and 1-transistor dynamic RAM
with necessary diagrams. June 2018 (R15)
4. Explain in detail about design flow of FPGA. June 2018 (R15)
5. Explain the working principle of 6-transistor Static RAM and 1-transistor Dynamic RAM
with necessary diagrams. Dec 2016 (R13)
6. (a) Draw and explain the architecture of a CPLD. Dec 2016 (R13)
(b)Differentiate between the Full-custom and Semi-custom design

7. (a) Write the differences between FPGA and CPLD. June 2016 (R13)
(b) Implement 4X4 Barrel shift register.

8. Implement arithmetic logic unit to perform both arithmetic and logic functions using a
full adder. June 2017 (R13)
9. Explain the design flow of FPGA. June 2016 (R13)
10. (a) Explain the 4 bit carry select adder.
(b) Construct a 4 bit Manchester carry chain adder June 2016(R09)
11. Implement 4X4 Array multiplier June 2014 (R09)
12. Implement the following using gate logic, June 2016 (R13)
(i) 4:1 multiplexer. (ii) 4-bit comparator. (iii) 8-bit parity generator June 2016 (R13)

PART-B

1. Explain about the architecture of a CLB

2. Explain the principle of gate arrays.
3. Define regularity? Explain the design of an ALU Subsystem.
 UNIT – V
1. (a) Write a short note on circuit synthesis. June 2018 (R15)
(b) Give comparison of design capture tools and design verification tools.
2. Explain in detail about design for testability. June 2018 (R15)
3. Explain the design capture and design verification tools. June 2018 (R15)
4. What is meant by synthesis? Explain the circuit synthesis design methods. June 2018
(R15).
5. Explain the design capture tools. Dec2016 (R13) & June 2017 (R13)
6. Explain the gate level and function level of testing. Dec 2016 (R13)
7. Explain the design verification tools.
8. (a) Write the VHDL code for full adder. June 2016 (R09)
(b) Explain about fault coverage.
9. (a) Design the principal and application of BST.
(b) Write about sequential logic testing. June 2016 (R09)
10. (a) Explain about fault simulation.
(b) Explain about simulation efficiency.
11. Discuss about the single stuck at fault.
12. What is testability? Discuss about the built in self-test.

PART-B

1. Describe the synthesis of VHDL code with examples.

2. Explain about Automatic Test Pattern Generation.
3. Explain about circuit level simulation and logic level simulation.