Faculty Aswan Faculty of Engineering Unit Code EE

Department Electrical Engineering Dep. Unit Title Experiment (5)

Year/ Year 3 Lecturer

Semester Semester 2 ( 2016-2017) Assistant

Course Digital Design Test(Digital) LAB Computers and Systems

Engineering Lab
Student name:……………………….. Evaluator
Eng: ………………………..
Date :………/………/……….
Mark: ……………../10

Experiment (5)

Flip-Flops and Synchronous Sequential Circuits

Main Goals
1-Provides an introduction to the SR latch.
2-Prepare the student for constructing, testing and investigating the operations
of various flip-flop circuits.
3-Provides an introduction to master-slave Flip-Flop.
4-Provides an introduction to Edge-Triggered Flip-Flop.
Objectives
To investigate the behavior of various flip-flop such as a D-Type Flip-Flop, a J-K
Flip-Flop and T flip-flop.
Theoretical background
A flip flop circuit can maintain a binary state indefinitely (as long as power
delivered to the circuit) until directed by an input signal to switch states. The
major differences among various types of flip-flops are in the number of inputs
they possess and in the manner in which the inputs affect the binary state.
A flip-flop circuit can be constructed from two NAND gates or NOR gates. Each
circuit forms a basic flip-flop upon which other more complicated types can be
built. The cross-coupled connection from the output of one gate to the input of
the other gate constitutes a feedback path. For this reason, the circuits are
classified as asynchronous sequential circuit. Each flip-flop has two outputs, Q
and Q', and two inputs, set and rest. This type of flip-flop is sometime called a
direct-coupled RS flip-flop, or SR latch.
To analyze the operation of the circuit of Figure 1 we must remember that the
output of a NOR gate is 0 if any inputs is 1, and that the output is 1 only when
all inputs are 0.

Lab Experiments 2nd Year Electric

When a 1 is applied to both the set and reset inputs, both Q and Q' outputs go to 0.
This condition violates the fact that the outputs Q and Q' are the complements of
each other. In normal operation, this condition must be avoided by making sure
that 1's are not applied to both inputs simultaneously.

S R Q Q'
1 0 1 0
0 0 1 0
0 1 0 1
0 0 0 1
1 1 0 0
Figure 1. Basic Latch Circuit with NOR Gate

The NAND basic latch circuit of Error! Reference source not found. operates
with both inputs normally at 1 unless the state of the latch has to be changed.
The application of a momentary 0 to the set input causes output Q to go to 1 and
Q' to go to 0, thus putting the latch into the set state. After the set input return to
1, a momentary 0 to the reset input causes a transition to the clear state. When
both inputs go to 0, both outputs go to 1.

S R Q Q'
1 0 0 1
1 1 0 1
0 1 1 0
1 1 1 0
0 0 1 1
Figure 2. Basic Latch Circuit with NAND Gate

RS Latch
The operation of the basic latch can be modified by providing an additional
control input that determines when the state of the circuit is to be changed. An
RS latch with a clock pulse (CP) input is shown in Figure 3.

Q S R Q(t+1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 Indeterminate
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 Indeterminate

Lab Experiments 2nd Year Electric

 Figure 3. Logic diagram and Characteristic table

D latch
One way to eliminate the undesirable condition of the indeterminate state in the
RS latch is to ensure that inputs S and R are never equal to 1 at the same time.
This is done in the D latch shown in Figure 4. The D latch has only two inputs:
D and CP. The D input goes directly to the S input and its complement is
applied to the R input.

Q D Q(t+1)
0 0 0
0 1 1
1 0 0
1 1 1

Figure 4. Logic Diagram and Characteristic table of D latch

Master-slave flip-flop
A master-slave flip-flop is constructed from two separate flip-flops. One circuit
serves as master and the other as a slave, and overall circuit is referred to as
master-slave flip-flop. The logic diagram of an RS master-slave flip-flop is
shown in Fig.5

Figure 5. Logic Diagram of a master-slave flip-flop

Edge-Triggered Flip-Flop
Another type of flip-flop that synchronizes the state changes during a clock-pulse
transition is the edge-triggered flip-flop. In this type output transitions occur at a
specific level of the clock pulse. When the pulse level exceeds this threshold level, the
inputs are locked out and the flip-flop is therefore unresponsive to further changes in

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inputs until the clock pulse return to 0 and another pulse occurs. some edge-triggered
flip-flops cause a transition on the positive edge of the pulse, and others cause a
transition on the negative edge of the pulse.
The logic diagram of a D-type positive-edge triggered flip-flop is shown in Fig.6

Figure 6. D-type positive-edge-triggered flip-flop

JK and T Flip-Flops
A JK flip-flop is a refinement of the RS flip-flop in that indeterminate state of the RS
type is defined in the JK type. Inputs J and K behave like inputs S and R to set and
clear the flip-flop, respectively. The input marked J is for set and the input marked K
is for reset. When both inputs J and K are equal to 1, the flip-flop switches to its
complement state.

Q J K Q(t+
1)
0 0 0 0
0 0 1 0
0 1 0 1
0 1 1 1
1 0 0 1
1 0 1 0
1 1 0 1
1 1 1 0
Figure 7. Logic Diagram and Characteristic table of JK flip-flop

The T flip-flop is a single-input version of the JK flip-flop. As shown in Figure 8

the T flip-flop is obtained from the JK flip-flop when both inputs are tied
together. The designation T comes from the ability of the flip-flop to "toggle,"
or complement, its state. Regardless of the present state, the flip-flop
complements its output when the clock pulse occurs while input T is 1.

Lab Experiments 2nd Year Electric

 Q T Q(t+1)
0 0 0
0 1 1
1 0 1
1 1 0

Figure 8. Logic Diagram and Characteristic table of T flip-flop

Equipments
IC chips 7410,7400,7402,7476,7474 .1
LEDs .2
Multimeter .3
Breadboard .4
Connecting wires .5
DC voltage supplies (5-Volts, 0-Volts0.6 )

7410 IC 7402 IC

7400 IC 7476 IC

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 7474 IC LED

Multimeter Breadboard

Connecting Wires 0-30V Power Supply

Exercises
Ex 5-1
RS latch

1- Construct a basic latch circuit (with NOR gate) shown in figure1 and
connect the two inputs to switches and the outputs to LEDs.
2- Obtain the truth table of the circuit.

R S Q Q'
0 0
0 1
1 0
1 1
Table

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 3- Construct a basic latch circuit(with NAND gate) shown in figure2 and
connect the two inputs to switches and the outputs to LEDs.
4- Obtain the truth table of the circuit.

R S Q Q'
0 0
0 1
1 0
1 1
Table
Ex 5-2
D latch
1. Construct a controlled D latch with four NAND gates as shown in figure
4.
2. With the power off connect the circuit
3. Switch on and confirm the circuits behavior and record the resultant
states Q and Q'

Q D Q(t+1)
0 0
0 1
1 0
1 1

Ex 5-3
IC 7474 D Flip-Flop

IC type 7474 consists of two D positive-edge-triggered flip-flops with preset

and clear.

Figure 9. IC 7474

1. Attach D, PRESET, and CLEAR to switches, the CLOCK input pin to

the Pulse generator, and Q and Q' to led.
2. With the power off connect the circuit

Lab Experiments 2nd Year Electric

 3. Switch the power on and fill out the results into the following table

Inputs Outputs
Preset Clear Clock D Q Q’
0 1 X X
1 0 X X
0 0 X X
1 1  0
1 1  1
1 1 0 X

Ex 5-4
IC 7476 JK Flip-Flop

IC type 7476 consists of two JK master-slaves JK Flip-Flop with

preset and clear.

Figure 2. IC 7476

1. Attach J, K, PRESET, and CLEAR to switches, the CLOCK input pin to the
Pulse generator, and Q and Q' to led.
2. Label the pin numbers in your circuit
3. With the power off connect the circuit
4. Switch the power on and fill out the results into the following table

PRESET CLEAR CLOCK J K Q Q’

0 1 OFF 0 0
1 0 OFF 0 0
0 0 OFF 0 0
1 1 ON 0 0
1 1 ON 1 0

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 1 1 ON 0 1
1 1 ON 1 1
1 1 ON 0 1

T Flip Flop:

Connect J and K together with switch to construct T flip-flop. Then fill out
the results into the following table:

Q T Q(t+1)
0 0
0 1
1 0
1 1

Ex 5-5
Counter with flip flops:

Design and implement an up/down odd counter that count from 0 to 7 with all
types of flip-flops D, JK, and T. An external input “u/d” is used to select the
direction of the count, 0 to count up and 1 to count down. The circuit is to be
designed by treating the unused states as don’t-care conditions. Show how the
problem that may raised form the unused states can be solved.

u/d A(t) A(t) C(t) A(t+1) B(t+1) C(t+1)

0 0 0 0
0 0 0 1
0 0 1 0
0 0 1 1
0 1 0 0
0 1 0 1
0 1 1 0
0 1 1 1
1 0 0 0
1 0 0 1
1 0 1 0
1 0 1 1
1 1 0 0
1 1 0 1
1 1 1 0
1 1 1 1

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Hint

1. Make sure that Vcc, are connected in right way and have a common
ground for each ICs and connect in the right pins.
2. Check the configuration of each IC by using the function for each
pin in the IC using IC's datasheet.
3. Check the fabrication of each IC to know power dissipation and the
maximum number of loaded ICs.
4. Each wire used in connection in experiment must be securely
connected and does not get crossed with other wires.
5. Make sure no short circuits occur between any two pins.
6. Check the direction and the arrangements of pins in ICs before
starting connecting the experiment.
7. The amplitude of the input/output signal must be kept in TTL range;
otherwise LEDs will not show any results.

Report
Design a sequential circuit with two (JK or T) flip-flops A and B and two
inputs E and F. If E = 0, the circuit remains in the same state regardless of the
value of F. When E = 1 and F = 1, the circuit goes through the state transitions
from 00 to 01, to 10, to 11, back to 00, and repeats. When E = 1 and F = 0, the
circuit goes through the state transitions from 00 to 11, to 10, to 01, back to 00,
and repeats.

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